JPS6413724U - - Google Patents
Info
- Publication number
- JPS6413724U JPS6413724U JP11023187U JP11023187U JPS6413724U JP S6413724 U JPS6413724 U JP S6413724U JP 11023187 U JP11023187 U JP 11023187U JP 11023187 U JP11023187 U JP 11023187U JP S6413724 U JPS6413724 U JP S6413724U
- Authority
- JP
- Japan
- Prior art keywords
- metal plate
- conductive layer
- semiconductor device
- semiconductor chip
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案の一実施例の電力半導体装置の
断面図、第２図及び第３図はそれぞれ本考案に用
いる金属ベース基板の異なる構造例を示す図であ
る。
１，５……金属板、２……プリント配線基板、
３……導電層、４……絶縁膜、６……接着剤、１
０……金属露出部、１１……半導体チツプ。
FIG. 1 is a sectional view of a power semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing different structural examples of metal base substrates used in the present invention, respectively. 1, 5...Metal plate, 2...Printed wiring board,
3... Conductive layer, 4... Insulating film, 6... Adhesive, 1
0...Metal exposed portion, 11...Semiconductor chip.
Claims (1)
け、前記金属板表面の金属露出部に半導体チツプ
を実装してなることを特徴とする電力半導体装置
。 1. A power semiconductor device comprising: a conductive layer provided on a part of the surface of a metal plate via an insulator; and a semiconductor chip mounted on an exposed metal portion of the surface of the metal plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11023187U JPS6413724U (en) | 1987-07-17 | 1987-07-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11023187U JPS6413724U (en) | 1987-07-17 | 1987-07-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6413724U true JPS6413724U (en) | 1989-01-24 |
Family
ID=31347201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11023187U Pending JPS6413724U (en) | 1987-07-17 | 1987-07-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6413724U (en) |
-
1987
- 1987-07-17 JP JP11023187U patent/JPS6413724U/ja active Pending