JPS61127665U - - Google Patents
Info
- Publication number
- JPS61127665U JPS61127665U JP1170885U JP1170885U JPS61127665U JP S61127665 U JPS61127665 U JP S61127665U JP 1170885 U JP1170885 U JP 1170885U JP 1170885 U JP1170885 U JP 1170885U JP S61127665 U JPS61127665 U JP S61127665U
- Authority
- JP
- Japan
- Prior art keywords
- insulating
- conductive
- dielectric material
- pattern
- pattern made
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims 4
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Description
第１図は、この考案の一実施例を示す要部断面
図、第２図は、第１図の概略平面図、第３図は従
来の混成厚膜集積回路基板を示す要部断面図であ
る。
図において、１は絶縁基板、２は第１の導体パ
ターン、３，４は絶縁パターン、５は第２の導体
パターン、６は第１の絶縁パターン、７は第２の
絶縁パターンである。なお、各図中同一符号は同
一または相当部分を示す。
FIG. 1 is a sectional view of a main part showing an embodiment of this invention, FIG. 2 is a schematic plan view of FIG. 1, and FIG. 3 is a sectional view of a main part showing a conventional hybrid thick film integrated circuit board. be. In the figure, 1 is an insulating substrate, 2 is a first conductor pattern, 3 and 4 are insulating patterns, 5 is a second conductor pattern, 6 is a first insulating pattern, and 7 is a second insulating pattern. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
基板において、絶縁基板上に、上記導電材料によ
る第１の導電パターンを形成してあり、次にこの
第１の導電パターン上に上記の誘電体材料を用い
て、所要面積の誘電体による第１の絶縁パターン
が形成してあつて、この第１の絶縁パターン上に
、この第１の絶縁パターンよりも面積が小さい誘
電体による第２の絶縁パターンを形成してあり、
さらに上記第１の導電パターン及び上記第１、第
２の絶縁パターン上に、上記の導電材料による第
２の導電パターンが形成してあることを特徴とす
る混成集積回路基板。 In a hybrid integrated circuit board using a conductive material and a dielectric material, a first conductive pattern made of the above conductive material is formed on an insulating substrate, and then the above dielectric material is formed on the first conductive pattern. A first insulating pattern made of a dielectric material having a required area is formed by using the method, and a second insulating pattern made of a dielectric material having a smaller area than the first insulating pattern is formed on this first insulating pattern. has been formed,
A hybrid integrated circuit board further comprising a second conductive pattern made of the conductive material described above and formed on the first conductive pattern and the first and second insulating patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1170885U JPS61127665U (en) | 1985-01-30 | 1985-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1170885U JPS61127665U (en) | 1985-01-30 | 1985-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61127665U true JPS61127665U (en) | 1986-08-11 |
Family
ID=30494078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1170885U Pending JPS61127665U (en) | 1985-01-30 | 1985-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127665U (en) |
-
1985
- 1985-01-30 JP JP1170885U patent/JPS61127665U/ja active Pending