JPH0425265U - - Google Patents
Info
- Publication number
- JPH0425265U JPH0425265U JP6657090U JP6657090U JPH0425265U JP H0425265 U JPH0425265 U JP H0425265U JP 6657090 U JP6657090 U JP 6657090U JP 6657090 U JP6657090 U JP 6657090U JP H0425265 U JPH0425265 U JP H0425265U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- circuit board
- integrated circuit
- substrate
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005259 measurement Methods 0.000 description 1
Description
第１図は、本考案の実施例を示す混成集積回路
基板の半完成状態の斜視図、第２図は、同混成集
積回路基板の特性測定時の要部斜視図、第３図は
、従来例を示す混成集積回路基板の特性測定時の
要部斜視図、第４図は、同じく従来例を示す混成
集積回路基板の特性測定時の側面図である。
１……基板、２……端子電極、３，４……導体
パターン、５……切欠部、５ａ……切欠部の導体
層、６ａ……スルーホール。
Fig. 1 is a perspective view of a semi-completed hybrid integrated circuit board showing an embodiment of the present invention, Fig. 2 is a perspective view of the main parts of the hybrid integrated circuit board during characteristic measurement, and Fig. 3 is a conventional one. FIG. 4 is a perspective view of a main part when measuring characteristics of a hybrid integrated circuit board showing an example, and FIG. 4 is a side view when measuring characteristics of a hybrid integrated circuit board, also showing a conventional example. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Terminal electrode, 3, 4...Conductor pattern, 5...Notch, 5a...Conductor layer in the notch, 6a...Through hole.
Claims (1)
ターンを有する混成集積回路基板において、基板
１の側面に切欠部５を有し、該切欠部５の壁面に
基板１の主面上の前記配線パターンの一部と導通
する導体層５ａが形成されたことを特徴とする混
成集積回路基板。 In a hybrid integrated circuit board having a wiring pattern made of a conductor layer on the main surface of an insulating substrate 1, a notch 5 is provided on the side surface of the substrate 1, and the wall surface of the notch 5 has a wiring pattern formed on the main surface of the substrate 1. A hybrid integrated circuit board characterized in that a conductor layer 5a is formed to be electrically connected to a part of a wiring pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6657090U JPH0425265U (en) | 1990-06-22 | 1990-06-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6657090U JPH0425265U (en) | 1990-06-22 | 1990-06-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0425265U true JPH0425265U (en) | 1992-02-28 |
Family
ID=31599391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6657090U Pending JPH0425265U (en) | 1990-06-22 | 1990-06-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0425265U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0946014A (en) * | 1995-07-28 | 1997-02-14 | Nec Toyama Ltd | Printed wiring board and product name check method |
-
1990
- 1990-06-22 JP JP6657090U patent/JPH0425265U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0946014A (en) * | 1995-07-28 | 1997-02-14 | Nec Toyama Ltd | Printed wiring board and product name check method |