JPS64364U - - Google Patents
Info
- Publication number
- JPS64364U JPS64364U JP9492987U JP9492987U JPS64364U JP S64364 U JPS64364 U JP S64364U JP 9492987 U JP9492987 U JP 9492987U JP 9492987 U JP9492987 U JP 9492987U JP S64364 U JPS64364 U JP S64364U
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- insulating substrate
- check
- contact pin
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
第１図ａ，ｂは本考案の一実施例の製造プロセ
スを示す上面図、第２図は本考案の一実施例の使
用状態を示す図である。
１……絶縁基板、２……チエツクランド、３…
…導体パターン、４……孔、５……はんだパター
ン、６……コンタクトピン。
FIGS. 1a and 1b are top views showing the manufacturing process of an embodiment of the present invention, and FIG. 2 is a diagram showing the state of use of the embodiment of the present invention. 1...Insulating substrate, 2...Checkland, 3...
...conductor pattern, 4...hole, 5...solder pattern, 6...contact pin.
Claims (1)
記導体パターンの一部をチエツクランドとしてコ
ンタクトピンにて導体パターンの電気的チエツク
を行なうプリント基板において、 上記チエツクランドをなす導体パターンからチ
エツクランド下の絶縁基板にチエツクランドより
小さくコンタクトピンより大きい穴を貫通させ、
該穴を覆つて上記絶縁基板主面上のチエツクラン
ドにはんだパターンを形成してなることを特徴と
するプリント基板。[Scope of Claim for Utility Model Registration] A printed circuit board in which a conductor pattern is formed on one main surface of an insulating substrate, and a part of the conductor pattern is used as a checkland to electrically check the conductor pattern with a contact pin, A hole smaller than the check land and larger than the contact pin is passed through the insulating substrate under the check land from the conductor pattern forming the
A printed circuit board characterized in that a solder pattern is formed on a check land on the main surface of the insulating substrate to cover the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9492987U JPS64364U (en) | 1987-06-18 | 1987-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9492987U JPS64364U (en) | 1987-06-18 | 1987-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS64364U true JPS64364U (en) | 1989-01-05 |
Family
ID=30958889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9492987U Pending JPS64364U (en) | 1987-06-18 | 1987-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS64364U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02109271U (en) * | 1989-02-16 | 1990-08-31 |
-
1987
- 1987-06-18 JP JP9492987U patent/JPS64364U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02109271U (en) * | 1989-02-16 | 1990-08-31 |