JPS63120430A - Method for preventing occurrence of crystal defect - Google Patents
Method for preventing occurrence of crystal defectInfo
- Publication number
- JPS63120430A JPS63120430A JP26820686A JP26820686A JPS63120430A JP S63120430 A JPS63120430 A JP S63120430A JP 26820686 A JP26820686 A JP 26820686A JP 26820686 A JP26820686 A JP 26820686A JP S63120430 A JPS63120430 A JP S63120430A
- Authority
- JP
- Japan
- Prior art keywords
- element isolation
- crystal defect
- isolation region
- region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013078 crystal Substances 0.000 title claims abstract description 38
- 230000007547 defect Effects 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 239000000356 contaminant Substances 0.000 claims abstract description 11
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052796 boron Inorganic materials 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 9
- 238000005247 gettering Methods 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000009279 wet oxidation reaction Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 241001174990 Boros Species 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は重金属等の汚染物をデバイス活性領域からゲッ
ターすることによシ、結晶欠陥発生を防止する方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for preventing crystal defect generation by gettering contaminants such as heavy metals from a device active region.
従来、この種のゲッタリング方法としては、単結晶基板
裏面に歪を導入したシして、デバイス活性領域の重金属
等をゲッタリングしていた。又SI単結晶基板において
は、8i単結晶基板中の酸素を析出させて、その析出物
とバルク8iとの歪によシ、デバイス活性領域の重金属
汚染物をゲッターしようという、いわゆるイントリンシ
ックゲッター(以後IG効果と記す)を使っていた。Conventionally, this type of gettering method involves introducing strain into the back surface of a single crystal substrate to getter away heavy metals and the like in the device active region. In addition, in the case of SI single crystal substrates, a so-called intrinsic getter (intrinsic getter) is used to precipitate oxygen in the 8i single crystal substrate and get heavy metal contaminants in the device active region by strain between the precipitates and the bulk 8i. (hereinafter referred to as the IG effect).
上述した従来のゲッタリング方法では、単結晶基板の裏
面歪ではデバイス製造途中の熱処理によシ導入した歪が
消滅し、ゲッタリング効果がデバイス製造工程の最終工
程まで保持できないという欠点がある。又IG効果では
デバイス製造工程の熱処理と単結晶基板中の酸素濃度に
よっては却って、結晶欠陥がデバイス活性領域に発生し
てしまいデバイスの歩留低下を招いてしまう。従って単
結晶基板の酸素濃度を厳しく管理する必要があシ種々の
熱処理の組合せで製造される種々のデバイスにおいては
、実用的でない。The above-described conventional gettering method has the disadvantage that the strain introduced by the heat treatment during device manufacturing disappears due to the strain on the back surface of the single crystal substrate, and the gettering effect cannot be maintained until the final step of the device manufacturing process. Moreover, in the IG effect, depending on the heat treatment in the device manufacturing process and the oxygen concentration in the single crystal substrate, crystal defects may occur in the device active region, resulting in a decrease in device yield. Therefore, it is necessary to strictly control the oxygen concentration of the single crystal substrate, which is not practical in various devices manufactured by combining various heat treatments.
本発明の結晶欠陥防止方法は、素子分離領域を形成する
工程において、結晶欠陥を選択的に素子分離領域に発生
させて、デバイス活性領域の重金属汚染物等をゲッター
することKJ:、!l)、デバイス活性領域の結晶欠陥
発生を防止する。The crystal defect prevention method of the present invention includes selectively generating crystal defects in the element isolation region in the step of forming the element isolation region to getter heavy metal contaminants, etc. in the device active region.KJ:,! l) Preventing the occurrence of crystal defects in the device active region.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
P型Sl単結晶基板1に酸化フォトリソグラフィーにて
N型拡散領域4を形成する。次にフォトリソグラフィー
にて酸化膜2を除去し、各素子の分離領域3を設け、素
子分離のための不純物としてボロン5を7 QKeV、
5 x l Ql’と−ズイオン注入する(第1図(a
))、素子分離不純物ボロン5を8i嘔結晶基板1に押
し込むために、 1.140°C90分湿式酸化法で
押し込むと、素子分離領域3には結晶欠陥が発生する。An N-type diffusion region 4 is formed on a P-type Sl single crystal substrate 1 by oxidation photolithography. Next, the oxide film 2 is removed by photolithography, isolation regions 3 are provided for each element, and boron 5 is added as an impurity for element isolation at 7 QKeV.
5 x l Ql' and -2 ions are implanted (see Figure 1 (a)
)) When the element isolation impurity boron 5 is forced into the 8i crystal substrate 1 by wet oxidation at 1.140° C. for 90 minutes, crystal defects are generated in the element isolation region 3.
次に通常のエピタキシャル成長工程にて81単結晶基板
1上にN型エピタキシャル1−7を形成する。その時素
子分離領域3には前記結晶欠陥が核となり、エピタキシ
ャル層7中に結晶欠陥8が形成される(第1図(b))
、以後通常のNPNTr製造工程に基づいてトランジス
ターを製造すれば、それら工程程にて混入してくる重金
属汚染物は、結晶欠陥8の歪場にゲッタリングされデバ
イス活性領域は汚染物がなくなり、デバイス歩留が向上
する。Next, an N-type epitaxial layer 1-7 is formed on the single crystal substrate 1 by a normal epitaxial growth process. At that time, the crystal defects become nuclei in the element isolation region 3, and crystal defects 8 are formed in the epitaxial layer 7 (FIG. 1(b)).
If a transistor is subsequently manufactured based on the normal NPNTr manufacturing process, the heavy metal contaminants mixed in during those processes will be gettered by the strain field of the crystal defect 8, and the device active region will be free of contaminants, and the device Yield is improved.
第2図は本発明の実施例2の縦断面図である。FIG. 2 is a longitudinal sectional view of Example 2 of the present invention.
N型埋込層4を有するP型巣結晶基板1にN型エピタキ
シャル/17を成長し、熱酸化にて酸化膜2を形成し、
フォトリソグラフィーによ多素子分離領域3を形成した
後Siを5 Q KeV l x l Q14)uズ注
入して8iイオン注入層9を形成する(第2図(a))
。次にボロンを素子分離領域3に1000°Cで熱拡散
して素子分離用ボロン層1oを形成する。An N-type epitaxial layer 17 is grown on a P-type nested crystal substrate 1 having an N-type buried layer 4, and an oxide film 2 is formed by thermal oxidation.
After forming the multi-element isolation region 3 by photolithography, Si is implanted in 5 Q KeV l x l Q14) to form an 8i ion implantation layer 9 (FIG. 2(a)).
. Next, boron is thermally diffused into the element isolation region 3 at 1000°C to form an element isolation boron layer 1o.
この時前記イオン注入されたS1層9は、S1単結晶中
で過剰となるので結晶欠陥8が形成される(第2図(b
))、以下通常のNPNTrの製造工程に基づいてトラ
ンジスターを製造すれば、結晶欠陥8により重金属等の
汚染物がゲッタリングされデバイスの特性2歩留は向上
する。At this time, the ion-implanted S1 layer 9 becomes excessive in the S1 single crystal, so crystal defects 8 are formed (Fig. 2(b)
)) If a transistor is manufactured based on the normal NPNTr manufacturing process, contaminants such as heavy metals are gettered by the crystal defects 8, and the yield of device characteristics 2 is improved.
以上説明したように、本発明は索子分離領域に結晶欠陥
を導入することにより、デバイス活性領域の重金属汚染
物をゲッターする効果があり、しかも製造工程途中に歪
場を与えるために1熱処理によって裏面束の様に消滅す
ることがなく、■G効果の様にS + ip結晶基板を
厳しく管理する必要がない。As explained above, the present invention has the effect of gettering heavy metal contaminants in the device active region by introducing crystal defects in the cord separation region, and also has the effect of gettering heavy metal contaminants in the device active region. It does not disappear like the backside bundle, and there is no need to strictly control the S + IP crystal substrate like the ■G effect.
第1図(aThlllB図(a)、(b)fd本%明o
素−1m領域へ結晶欠陥を導入するための工種断面図で
ある。
1・・・・・・Si単結晶基板、2・・・・・・酸化膜
、3・・・・・・素子分離領域、4・・・・・・N型埋
込拡散層、5・・・・・・イオン注入ボロン層、6・・
・・・・埋込ボロン層、7・旧・・N型エビタギシャル
層、8・・・・・・エピタキシャル層内の素子分離領域
の結晶欠陥、9・旧・・イオン注入81#、10・・・
・・・素子分離用拡散ボロ7層。
矛 1 凹Figure 1 (aThllllB figure (a), (b) fd book % bright o
FIG. 2 is a cross-sectional view of a process for introducing crystal defects into an element-1m region. DESCRIPTION OF SYMBOLS 1... Si single crystal substrate, 2... Oxide film, 3... Element isolation region, 4... N-type buried diffusion layer, 5... ...Ion-implanted boron layer, 6...
...Buried boron layer, 7. Old... N-type epitaxial layer, 8... Crystal defects in element isolation region in epitaxial layer, 9. Old... Ion implantation 81#, 10...・
...7 layers of diffusion boros for element isolation. spear 1 concave
Claims (1)
ス活性領域の重金属汚染物等をゲッターすることを特徴
とする結晶欠陥防止方法。A method for preventing crystal defects, characterized in that heavy metal contaminants, etc. in a device active region are gettered by generating crystal defects in an element isolation region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26820686A JPS63120430A (en) | 1986-11-10 | 1986-11-10 | Method for preventing occurrence of crystal defect |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26820686A JPS63120430A (en) | 1986-11-10 | 1986-11-10 | Method for preventing occurrence of crystal defect |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63120430A true JPS63120430A (en) | 1988-05-24 |
Family
ID=17455393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26820686A Pending JPS63120430A (en) | 1986-11-10 | 1986-11-10 | Method for preventing occurrence of crystal defect |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63120430A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02156540A (en) * | 1988-12-08 | 1990-06-15 | Nec Corp | Manufacture of semiconductor device |
JPH05110053A (en) * | 1991-10-14 | 1993-04-30 | Matsushita Electron Corp | Solid-state imaging device and manufacture thereof |
-
1986
- 1986-11-10 JP JP26820686A patent/JPS63120430A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02156540A (en) * | 1988-12-08 | 1990-06-15 | Nec Corp | Manufacture of semiconductor device |
JPH05110053A (en) * | 1991-10-14 | 1993-04-30 | Matsushita Electron Corp | Solid-state imaging device and manufacture thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2806277B2 (en) | Semiconductor device and manufacturing method thereof | |
JPS63120430A (en) | Method for preventing occurrence of crystal defect | |
JPH06216137A (en) | Semiconductor device and manufacture thereof | |
JPH05235005A (en) | Semiconductor substrate and manufacture thereof | |
JP2743452B2 (en) | Method for manufacturing semiconductor device | |
JP3282265B2 (en) | Method for manufacturing semiconductor device | |
JPS6362326A (en) | Manufacture of semiconductor device | |
JPS63271941A (en) | Prevention of occurrence of crystal defect | |
JPH01760A (en) | Manufacturing method of semiconductor device | |
JPS59175721A (en) | Manufacture of semiconductor device | |
JPH1187258A (en) | Manufacture of semiconductor device | |
JP3756617B2 (en) | Manufacturing method of semiconductor device | |
JPH0479216A (en) | Manufacture of mis type semiconductor device | |
JPH04309226A (en) | Manufacture of semiconductor device | |
JPS60173844A (en) | Manufacture of semiconductor element | |
JPH01297837A (en) | Manufacture of semiconductor device | |
JPH03138927A (en) | Manufacture of semiconductor device | |
JPH03222427A (en) | Semiconductor device | |
JPS59119761A (en) | Manufactuer of semiconductor device | |
KR20000003939A (en) | Method for manufacturing semiconductor devices | |
JPH03217019A (en) | Manufacture of semiconductor device | |
JPH0254539A (en) | Manufacture of vertical mos-fet | |
JPS58153337A (en) | Manufacture of semiconductor device | |
JPS58106835A (en) | Manufacture of semiconductor device | |
JPH02105410A (en) | Manufacture of semiconductor device |