JPH01760A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH01760A JPH01760A JP62-155692A JP15569287A JPH01760A JP H01760 A JPH01760 A JP H01760A JP 15569287 A JP15569287 A JP 15569287A JP H01760 A JPH01760 A JP H01760A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- oxide film
- manufacturing
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来の半導体装置、特にゲート電極が酸化膜サイドウオ
ールを存し、ソース、ドレイン及びゲート電極上にメタ
ルシリサイドを存する半導体装置（以下サリサイド構造
の半導体装置と略記する）の製造方法の一例を第２図に
示す。An example of a manufacturing method for a conventional semiconductor device, particularly a semiconductor device in which the gate electrode has an oxide film sidewall and metal silicide is present on the source, drain, and gate electrodes (hereinafter abbreviated as a semiconductor device with a salicide structure) is described in the second example. As shown in the figure.
工程（＋１・・・第２図１ｌｌ
Ｐ型半導体基板２０１上に周知の技術により、素子分離
用酸化膜２０２、ゲート酸化膜２０３、ゲート電極２０
４、低濃度Ｎ型不純物拡散層２゜５、酸化膜サイドウオ
ール２０６を形成する。Process (+1...FIG. 2 1ll) An oxide film 202 for element isolation, a gate oxide film 203, a gate electrode 20 are formed on a P-type semiconductor substrate 201 by a well-known technique.
4. Form a low concentration N-type impurity diffusion layer 2.5 and an oxide film sidewall 206.
工程（２）・・・第２図１ｂ＋
イオン注入透過ｖ！、 ２０７を熱酸化法で形成した後
、高濃度Ｎ！不純物をイオン注入し、熱アニールにより
ソース・ドレイン拡散層２０８を形成する。Step (2)...Figure 2 1b+ Ion implantation transmission v! , 207 by a thermal oxidation method, and then high concentration N! Impurity ions are implanted and thermal annealing is performed to form source/drain diffusion layers 208.
工程（３）・・・第２図（Ｃ１
前記イオン注入透過膜２０７をＨＦで除去した後、メタ
ルをスパッタ法で形成し、熱アニール、及び選択エッチ
により、前記ゲート電極２０４及び前記ソース・ドレイ
ン２０８上にメタルシリサイド２０９を形成する。Step (3)...FIG. 2 (C1) After removing the ion-implanted permeable film 207 with HF, metal is formed by sputtering, and thermal annealing and selective etching are performed to form the gate electrode 204 and the source/drain. Metal silicide 209 is formed on 208.
しかし、前述の従来技術では、工程（３）で述べたよう
にメタルを形成する前にイオン注入透過膜を除去する必
要があり、その時、工程（１）で形成された酸化膜サイ
ドウオールの一部が除去される。However, in the prior art described above, it is necessary to remove the ion implantation permeable film before forming the metal as described in step (3), and at that time, part of the oxide film sidewall formed in step (1) is removed. part is removed.
サリサイド構造の半導体装置においては、この酸化膜サ
イドウオールは、ソース拳ドレインの分濫の役目を果た
すものであり、第３図に示したようにサイドウオール酸
化膜３ｏ６の減少は、ソース拳ドレイン３０８とゲート
電極３０４のショートにつながるという問題があった。In a semiconductor device with a salicide structure, this oxide film sidewall plays the role of dividing the source fist and drain, and as shown in FIG. There is a problem in that this leads to a short circuit of the gate electrode 304.
そこで本発明はこのような問題点を解決するもので、そ
の目的とすることは、サイドウオール酸化膜の減少を防
ぎ、ソース・ドレインどゲート電極のショートのないサ
リサイド構造の半導体装置の製造方法を提供することに
ある。The present invention is intended to solve these problems, and its purpose is to provide a method for manufacturing a semiconductor device with a salicide structure that prevents the reduction of the sidewall oxide film and prevents short-circuiting of the source, drain, and gate electrodes. It is about providing.
１）本発明の半導体Ｒ’ ｉｌの製造方法は、ゲート電
極が酸化膜サイドウオールを存するサリサイド構造の半
導体装置の製造にあたり、高濃度不純物のイオン注入透
過膜にシリコンナイトライド膜を用いることを特徴とす
る。1) The method for manufacturing a semiconductor R' il of the present invention is characterized in that a silicon nitride film is used as a permeable film for ion implantation of high concentration impurities when manufacturing a semiconductor device having a salicide structure in which a gate electrode has an oxide film sidewall. shall be.
以下第１図により詳細に実施例を説明する。 An embodiment will be described in detail below with reference to FIG.
工程（１）・・・第１図（ａｌ
Ｐｕ半導体基板１０１上に周知の技術により、素子分離
用酸化膜１０２、ゲート酸化１Ｘｔａ３、ゲート電極１
０５、低濃度Ｎ型不純物拡散層１０５、酸化膜サイドウ
オール１０６を形成する。Step (1)...FIG. 1 (An oxide film 102 for element isolation, a gate oxide 1
05, a low concentration N-type impurity diffusion layer 105 and an oxide film sidewall 106 are formed.
工程（２）・・・第１図ｆａｔ
化学的気相成長法によりシリコンナイトライド膜１０７
を１００〜３００人形成し、これをイオン注入透過膜と
する。Step (2)...Figure 1 fat silicon nitride film 107 by chemical vapor deposition method
100 to 300 people are formed, and this is used as an ion implantation permeable membrane.
工程（３）・・・第１図（Ｃ１
前記シリコンナイトライド膜１０７を通し、高濃ａ′Ｎ
型不純物を前記Ｐ型半導体基板１０１にイオン注入し、
９００〜９５０°Ｃの熱処理によりソース・ドレイン拡
散ＦＪＪ１０８を形成する。Step (3)...Figure 1 (C1 Highly concentrated a'N is passed through the silicon nitride film 107.
ion-implanting type impurities into the P-type semiconductor substrate 101;
A source/drain diffusion FJJ 108 is formed by heat treatment at 900 to 950°C.
工程（４）・・・第１図ｆｄｌ
前記シリコンナイトライド膜１０７を熱リン酸で除去す
る。Step (4)...FIG. 1 fdl The silicon nitride film 107 is removed with hot phosphoric acid.
工程（９・・・ｉｆ図ｔｅｌ
Ｔｉ、Ｃｏ、Ｗ等のメタルをスパッタ法で４゜０〜６０
０人形成し、ハロゲンランプで６０００Ｃ〜７００°Ｃ
ｌ２Ｏ秒〜３０秒で熱処理し、前記ゲート電極１０４上
、及び前記ソース・ドレイン拡散８！０８上のみにメタ
ルシリサイド１０９を形成する。この時、前記素子分離
用酸化膜１゜２及び前記酸化膜サイドウオール１０６上
のメタルはシリサイド化されないため、アンモニア、過
酸化水素、水の混合液により容易に除去される。Process (9...if figure tel) Metals such as Ti, Co, and W are sputtered at 4°0 to 60°.
Formed by 0 people and heated to 6000C to 700°C with a halogen lamp.
A heat treatment is performed for 120 seconds to 30 seconds to form metal silicide 109 only on the gate electrode 104 and the source/drain diffusions 8!08. At this time, since the metal on the element isolation oxide film 1.2 and the oxide film sidewall 106 is not silicided, it is easily removed by a mixed solution of ammonia, hydrogen peroxide, and water.
工程（６）・・・第１図（「）
１■３己メタルシリサイド１０９をハロゲンランプで８
００°Ｃ〜９００°０１２０秒〜３０秒で短時間熱処理
することで、 ダイシリサイド化を行い、周知の方法で
層間絶縁膜１１０、コンタクトホール１１１、配線材料
Ａβ１１２を形成する。Step (6)...Figure 1 ('')
By performing a short heat treatment at 00° C. to 900° C.0120 seconds to 30 seconds, disiliciding is performed, and an interlayer insulating film 110, a contact hole 111, and a wiring material Aβ 112 are formed by a well-known method.
以上述べたように本発明によれば、ソース・ドレイン拡
散層形成のためのイオン注入透過膜に用いたシリコンナ
イトライド膜は、熱リン酸で容易に除去され、また酸化
膜は熱リン酸にエツチングされないため、既に形成され
ていた酸化膜サイドウオールの減少は回避できる。 こ
のため、ソース・ドレインは、ゲート電極のショートが
全くない、優れたサリサイド構造の半導体装置が製造さ
れる。As described above, according to the present invention, the silicon nitride film used as the ion-implanted permeable film for forming the source/drain diffusion layer can be easily removed with hot phosphoric acid, and the oxide film can be easily removed with hot phosphoric acid. Since it is not etched, reduction of the oxide film sidewall that has already been formed can be avoided. Therefore, a semiconductor device with an excellent salicide structure is manufactured in which the source/drain has no short circuit at the gate electrode.
第１図ｆａｔ〜（「）は本発明の実施例を示す半導体装
置の製造工程を表わす主要製造工程断面図。第２図（ａ
ｌ〜ｔｃ＋は従来の半導体装置の製造工程を表わす主要
製造工程断面図。
第３図は、従来の半導体装置の欠点を表わす断面図。
１０１．２０１，３０１・・・・・・Ｐ型半導体基板１
０２．２０２・・・・・・素子分離用酸化膜１０３、２
０３．３０３・−−−−−ケ−）ｆｆｉ化膜１０４．２
０４，３０４・・・・・・ゲート電極１０５．２０５，
３０５・・・・・・低濃度Ｎ型不純物拡散層
１０６．２０８，３０６・・・・・・酸化膜サイドゥオ
−ル
１０７・・・・・・シリコンナイトライド膜２０７・・
・・・・イオン注入透過膜。
１０８．２０８，３０８・・・・・・ソース・ドレイ／
拡散層
１０９．２０９，３０９・・・・・・メタルシリサイド
１１０・・・・・・層間絶縁膜
１１１・・・・・・コンタクトホール
１１２・・・・・・配線材料用Ａρ
以 上
出願人 セイコーエプソン株式会社 ゛代理人 弁理
士 最 上 務 他１名゛ノ
（ｂ）
ｌσｔ
（Ｃ）
１１凹
（＋）
１ ｉ 揖
（Ｃ）
１ 込 摺Fig. 1 (fat) is a cross-sectional view of the main manufacturing process showing the manufacturing process of a semiconductor device showing an embodiment of the present invention. Fig. 2 (a)
1 to tc+ are main manufacturing process cross-sectional views showing the manufacturing process of a conventional semiconductor device. FIG. 3 is a cross-sectional view showing the drawbacks of a conventional semiconductor device. 101.201,301...P-type semiconductor substrate 1
02.202... Oxide film for element isolation 103, 2
03.303・------K-)ffi film 104.2
04,304...Gate electrode 105.205,
305...Low concentration N-type impurity diffusion layer 106, 208, 306...Oxide film sidewall 107...Silicon nitride film 207...
...Ion implantation permeable membrane. 108.208,308...Sauce Dray/
Diffusion layer 109, 209, 309...Metal silicide 110...Interlayer insulating film 111...Contact hole 112...Aρ for wiring material Applicant Seiko Epson Corporation ゛Agent Patent attorney Tsutomu Mogami and 1 other person゛ノ(b) lσt (C) 11 concave (+) 1 i 揖(C) 1 included
Claims (1)
、ドレイン及びゲート電極上にメタルシリサイドを有す
る半導体装置の製造方法において、高濃度不純物のイオ
ン注入透過膜にシリコンナイトライド膜を用いることを
特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which the gate electrode has an oxide film sidewall and metal silicide on the source, drain, and gate electrodes, characterized in that a silicon nitride film is used as the ion implantation permeable film of high concentration impurities. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-155692A JPH01760A (en) | 1987-06-23 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-155692A JPH01760A (en) | 1987-06-23 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS64760A JPS64760A (en) | 1989-01-05 |
| JPH01760A true JPH01760A (en) | 1989-01-05 |
Family
ID=
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