JPS6310895B2 - - Google Patents

Info

Publication number
JPS6310895B2
JPS6310895B2 JP57075166A JP7516682A JPS6310895B2 JP S6310895 B2 JPS6310895 B2 JP S6310895B2 JP 57075166 A JP57075166 A JP 57075166A JP 7516682 A JP7516682 A JP 7516682A JP S6310895 B2 JPS6310895 B2 JP S6310895B2
Authority
JP
Japan
Prior art keywords
layer
silicon
active region
void
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57075166A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58192345A (ja
Inventor
Mutsunobu Arita
Nobuyoshi Awaya
Masaaki Sato
Michiharu Tanabe
Kazuto Sakuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7516682A priority Critical patent/JPS58192345A/ja
Publication of JPS58192345A publication Critical patent/JPS58192345A/ja
Publication of JPS6310895B2 publication Critical patent/JPS6310895B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
JP7516682A 1982-05-07 1982-05-07 半導体装置の製造方法 Granted JPS58192345A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7516682A JPS58192345A (ja) 1982-05-07 1982-05-07 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7516682A JPS58192345A (ja) 1982-05-07 1982-05-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58192345A JPS58192345A (ja) 1983-11-09
JPS6310895B2 true JPS6310895B2 (enrdf_load_stackoverflow) 1988-03-10

Family

ID=13568338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7516682A Granted JPS58192345A (ja) 1982-05-07 1982-05-07 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58192345A (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61125039A (ja) * 1984-11-21 1986-06-12 Nec Corp 半導体装置の製造方法
JPS61198743A (ja) * 1985-02-28 1986-09-03 New Japan Radio Co Ltd 半導体装置の製造方法
JPH0799758B2 (ja) * 1985-07-05 1995-10-25 松下電器産業株式会社 半導体装置およびその製造方法
US4888300A (en) * 1985-11-07 1989-12-19 Fairchild Camera And Instrument Corporation Submerged wall isolation of silicon islands
JP4862253B2 (ja) * 2004-09-28 2012-01-25 セイコーエプソン株式会社 半導体基板の製造方法及び半導体装置の製造方法
US8426289B2 (en) * 2011-04-14 2013-04-23 Robert Bosch Gmbh Wafer with spacer including horizontal member

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50102276A (enrdf_load_stackoverflow) * 1974-01-09 1975-08-13

Also Published As

Publication number Publication date
JPS58192345A (ja) 1983-11-09

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