JPS63108648U - - Google Patents
Info
- Publication number
- JPS63108648U JPS63108648U JP20381186U JP20381186U JPS63108648U JP S63108648 U JPS63108648 U JP S63108648U JP 20381186 U JP20381186 U JP 20381186U JP 20381186 U JP20381186 U JP 20381186U JP S63108648 U JPS63108648 U JP S63108648U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead frame
- resin package
- semiconductor device
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の半導体装置の一例を示す断面
図、第２図は本考案の半導体装置の他の一例を示
す断面図、第３図は従来の半導体装置の部分断面
図である。 １，１１…梨地面、２，１２…リードフレーム
、３，１３…ダイパツド部、４，１４…樹脂パツ
ケージ、５，１５…チツプ、６，１６…外部端子
。
図、第２図は本考案の半導体装置の他の一例を示
す断面図、第３図は従来の半導体装置の部分断面
図である。 １，１１…梨地面、２，１２…リードフレーム
、３，１３…ダイパツド部、４，１４…樹脂パツ
ケージ、５，１５…チツプ、６，１６…外部端子
。
Claims (1)
- 【実用新案登録請求の範囲】 集積回路が形成されるチツプと、そのチツプを
載置するためのリードフレームと、これらチツプ
及びリードフレームを封止する樹脂パツケージと
を具備するものにおいて、 上記リードフレームは、少なくとも上記樹脂パ
ツケージとの接着面の全部又は一部が梨地面とさ
れることを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20381186U JPS63108648U (ja) | 1986-12-27 | 1986-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20381186U JPS63108648U (ja) | 1986-12-27 | 1986-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63108648U true JPS63108648U (ja) | 1988-07-13 |
Family
ID=31169491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20381186U Pending JPS63108648U (ja) | 1986-12-27 | 1986-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63108648U (ja) |
-
1986
- 1986-12-27 JP JP20381186U patent/JPS63108648U/ja active Pending
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