JPS6259821B2 - - Google Patents

Info

Publication number
JPS6259821B2
JPS6259821B2 JP54006485A JP648579A JPS6259821B2 JP S6259821 B2 JPS6259821 B2 JP S6259821B2 JP 54006485 A JP54006485 A JP 54006485A JP 648579 A JP648579 A JP 648579A JP S6259821 B2 JPS6259821 B2 JP S6259821B2
Authority
JP
Japan
Prior art keywords
address
data
transfer
memory
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54006485A
Other languages
English (en)
Japanese (ja)
Other versions
JPS54121032A (en
Inventor
Deii Horubaajaa Kenesu
Ii Samuson Josefu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of JPS54121032A publication Critical patent/JPS54121032A/ja
Publication of JPS6259821B2 publication Critical patent/JPS6259821B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
JP648579A 1978-01-23 1979-01-23 Data processor using high speed data channel Granted JPS54121032A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87169078A 1978-01-23 1978-01-23

Publications (2)

Publication Number Publication Date
JPS54121032A JPS54121032A (en) 1979-09-19
JPS6259821B2 true JPS6259821B2 (sv) 1987-12-12

Family

ID=25357925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP648579A Granted JPS54121032A (en) 1978-01-23 1979-01-23 Data processor using high speed data channel

Country Status (12)

Country Link
JP (1) JPS54121032A (sv)
AU (1) AU526317B2 (sv)
BR (1) BR7900407A (sv)
CA (1) CA1128213A (sv)
CH (1) CH641581A5 (sv)
DE (1) DE2902477A1 (sv)
DK (1) DK157954C (sv)
FR (1) FR2415336B1 (sv)
GB (1) GB2013006B (sv)
IT (1) IT1110622B (sv)
NL (1) NL7900439A (sv)
SE (1) SE444996B (sv)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4459677A (en) * 1980-04-11 1984-07-10 Ampex Corporation VIQ Computer graphics system
US4476527A (en) * 1981-12-10 1984-10-09 Data General Corporation Synchronous data bus with automatically variable data rate
GB2138182B (en) * 1983-04-14 1986-09-24 Standard Telephones Cables Ltd Digital processor
US4607365A (en) * 1983-11-14 1986-08-19 Tandem Computers Incorporated Fault-tolerant communications controller system
US4847750A (en) * 1986-02-13 1989-07-11 Intelligent Instrumentation, Inc. Peripheral DMA controller for data acquisition system
JP2570847B2 (ja) * 1989-02-08 1997-01-16 日本電気株式会社 データ転送方式
CN108241516B (zh) * 2018-02-09 2021-06-18 深圳科立讯通信有限公司 嵌入式系统程序加载方法、装置、计算机设备和存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522231A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus
JPS5272543A (en) * 1975-12-15 1977-06-17 Hitachi Ltd Channel equipment of having address converting function

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673576A (en) * 1970-07-13 1972-06-27 Eg & G Inc Programmable computer-peripheral interface
GB1447297A (en) * 1972-12-06 1976-08-25 Amdahl Corp Data processing system
US3976977A (en) * 1975-03-26 1976-08-24 Honeywell Information Systems, Inc. Processor for input-output processing system
US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522231A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus
JPS5272543A (en) * 1975-12-15 1977-06-17 Hitachi Ltd Channel equipment of having address converting function

Also Published As

Publication number Publication date
DE2902477A1 (de) 1979-07-26
CA1128213A (en) 1982-07-20
CH641581A5 (de) 1984-02-29
AU526317B2 (en) 1983-01-06
GB2013006B (en) 1982-08-25
IT1110622B (it) 1985-12-23
GB2013006A (en) 1979-08-01
DK3979A (da) 1979-07-24
BR7900407A (pt) 1979-08-21
DK157954C (da) 1990-08-13
SE444996B (sv) 1986-05-20
IT7919549A0 (it) 1979-01-23
FR2415336A1 (fr) 1979-08-17
JPS54121032A (en) 1979-09-19
SE7900138L (sv) 1979-07-24
FR2415336B1 (fr) 1987-04-24
AU4322779A (en) 1979-08-02
NL7900439A (nl) 1979-07-25
DK157954B (da) 1990-03-05

Similar Documents

Publication Publication Date Title
US4403282A (en) Data processing system using a high speed data channel for providing direct memory access for block data transfers
US4169284A (en) Cache control for concurrent access
US4550368A (en) High-speed memory and memory management system
US5613162A (en) Method and apparatus for performing efficient direct memory access data transfers
US5524268A (en) Flexible processor-driven control of SCSI buses utilizing tags appended to data bytes to determine SCSI-protocol phases
US5379384A (en) Configuration data loopback in a bus bridge circuit
US5289585A (en) Multiprocessor system having a system bus for the coupling of several processing units with appertaining private cache memories and a common main memory
US6272582B1 (en) PCI-PCI bridge allowing controlling of a plurality of PCI agents including a VGA device
US6282589B1 (en) System for sharing data buffers from a buffer pool
US6189062B1 (en) Apparatus and method for address translation in bus bridge devices
JP2853809B2 (ja) 周辺コントローラのためのバッファメモリサブシステムおよび方法
JP2004110785A (ja) メモリコントローラ
US4949247A (en) System for transferring multiple vector data elements to and from vector memory in a single operation
JPS6259821B2 (sv)
US6161153A (en) Method for sharing data buffers from a buffer pool
US5983266A (en) Control method for message communication in network supporting software emulated modules and hardware implemented modules
JPH0793274A (ja) データ転送方式及びデータ転送装置
US6327636B1 (en) Ordering for pipelined read transfers
JP3251903B2 (ja) プロセッサ・データをバースト転送する方法及びコンピュータ・システム
US7039735B2 (en) Direct slave addressing to indirect slave addressing
US20030200358A1 (en) Method, apparatus, and system for maintaining conflict-free memory address space for input/output memory subsystems
US20010002481A1 (en) Data access unit and method therefor
JPS61150054A (ja) データ処理装置
JPH10283302A (ja) 複数のプロセッサに接続されたバスにデータを供給する方法およびシステム
JPH02171843A (ja) インターフェース装置