JPS6242548B2 - - Google Patents

Info

Publication number
JPS6242548B2
JPS6242548B2 JP56071113A JP7111381A JPS6242548B2 JP S6242548 B2 JPS6242548 B2 JP S6242548B2 JP 56071113 A JP56071113 A JP 56071113A JP 7111381 A JP7111381 A JP 7111381A JP S6242548 B2 JPS6242548 B2 JP S6242548B2
Authority
JP
Japan
Prior art keywords
frame
transmission
address
signal
flag sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56071113A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57185750A (en
Inventor
Akihiko Ootani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP56071113A priority Critical patent/JPS57185750A/ja
Publication of JPS57185750A publication Critical patent/JPS57185750A/ja
Publication of JPS6242548B2 publication Critical patent/JPS6242548B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/0078Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083Formatting with frames or packets; Protocol or part of protocol for error control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
JP56071113A 1981-05-11 1981-05-11 Transmission system Granted JPS57185750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56071113A JPS57185750A (en) 1981-05-11 1981-05-11 Transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56071113A JPS57185750A (en) 1981-05-11 1981-05-11 Transmission system

Publications (2)

Publication Number Publication Date
JPS57185750A JPS57185750A (en) 1982-11-16
JPS6242548B2 true JPS6242548B2 (enExample) 1987-09-09

Family

ID=13451173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56071113A Granted JPS57185750A (en) 1981-05-11 1981-05-11 Transmission system

Country Status (1)

Country Link
JP (1) JPS57185750A (enExample)

Also Published As

Publication number Publication date
JPS57185750A (en) 1982-11-16

Similar Documents

Publication Publication Date Title
JPS61100046A (ja) ル−プ伝送方法
JPS6242548B2 (enExample)
JPH0221619B2 (enExample)
EP0185093A1 (en) Data transfer equipment
JP2001202345A (ja) 並列プロセッサ
JPH026263B2 (enExample)
JPS59134943A (ja) デ−タ通信システム
JPS5955657A (ja) 回線走査方式
JPS6153985B2 (enExample)
JPH02143639A (ja) パケット長変換方式
SU1278871A1 (ru) Устройство дл сопр жени микропроцессорных внешних устройств с каналом ввода-вывода ЭВМ
JPH01168136A (ja) 電子交換機
US20030067937A1 (en) System for transmitting data between modules and method for controlling the same
JPS61200734A (ja) デ−タ伝送方式
JPH0650478B2 (ja) デ−タ圧縮記憶方式
JPH02272843A (ja) データ伝送装置
JPS61198351A (ja) ダイレクト・メモリ・アクセス制御回路
JPS6132629A (ja) 多回線通信制御方法
JPH0636517B2 (ja) パケツト通信における受信バツフア決定方式
JPS63215242A (ja) デ−タ収集方式
JPS6314538B2 (enExample)
JPS61285850A (ja) スロツト・リング型通信制御方式
JPS6050094B2 (ja) データバス方式
JPS6191755A (ja) デ−タ伝送制御方式
JPS6238636A (ja) マルチドロツプにおける送信権獲得方式