JPS6222532B2 - - Google Patents

Info

Publication number
JPS6222532B2
JPS6222532B2 JP56170396A JP17039681A JPS6222532B2 JP S6222532 B2 JPS6222532 B2 JP S6222532B2 JP 56170396 A JP56170396 A JP 56170396A JP 17039681 A JP17039681 A JP 17039681A JP S6222532 B2 JPS6222532 B2 JP S6222532B2
Authority
JP
Japan
Prior art keywords
lead frame
clad
package
plate
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56170396A
Other languages
English (en)
Other versions
JPS5871645A (ja
Inventor
Nobuo Ogasa
Akira Ootsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP56170396A priority Critical patent/JPS5871645A/ja
Publication of JPS5871645A publication Critical patent/JPS5871645A/ja
Publication of JPS6222532B2 publication Critical patent/JPS6222532B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明はガラス封止型のいわゆるサーデインプ
型IC用パツケージに用いられるリードフレーム
素材のAlクラツド板に関する。
近年、ICの高集積度化が進む一方容量の増大
が進み、パツケージ自体の大きさは縮少傾向にあ
り、必然的にガラス封止部の面積の縮少が余儀な
くされている。各種パツケージの中でサーデイツ
プ型ICパツケージも多用されており高信頼性と
低コスト化が強く要望されている。
このICパツケージのICと外部回路の接続に使
用されるリードフレームの素材として、従来第１
図にその斜視拡大図を示す如く、Fe−Ni合金１
の１表面中央部にAl２がクラツドされたAlクラ
ツド板が用いられている。このAlクラツド板を
所定形状に金型によつて打抜き、第２図に示す様
に、リードフレーム５として利用される。基板３
上に塔載されたICチツプ４とリードフレームの
Al部７の間がAlワイヤー８によつてボンデング
されている。そして基板、上蓋及びリードフレー
ムは低融点ガラス６によつて封止される。サーデ
イツプのガラス封止機構は、金属表面の酸化物層
とガラスの相互拡散によるものであるが、封止温
度が低温である為、気密性を保証するためにはガ
ラス封止面積の確保が重要である。一方上述の如
くパツケージの小型化の要望も強く、その両方を
満足するためには従来のリードフレーム用Alク
ラツド板では不充分となつて来た。
本発明はこの問題を解消せんとするものであり
パツケージの小型化による封止面積の縮少に対処
し得るAlクラツド板を提供するものである。
すなわち、第３図に本発明のAlクラツド板の
断面を示す如く、Fe−Ni合金１の表面部にAl部
９をクラツドし、その両側に凹部１０を設けるこ
とによつて封止部の接触面積の増大を計るもので
ある。
あるいは第４図に示す如く、Alクラツド面及
び反対面の凹部表面に、下地の密着性の良いFe
−Al合金層１１を介在させ接触面積増大以外に
拡散促進も計ることができるものである。
封止部表面積を増大させる方法として、従来、
表面粗さを粗くするためブラツシユ研摩等のメカ
ニカルな方法があるが、寸法精度の問題があるば
かりでなく、研摩粉の残存による表面汚染が、ガ
ラス封止後の気密性の要因となるほど実用上問題
があつた。
本発明品はこのような問題を解消するものであ
る。ガラス封止部にAlを残す考えもあるが、Al
は封止ガラスとの熱膨張係数の差が大きく、封止
部からはみ出すとエレクトロ・マイグレーシヨン
やAlの腐食などの問題が生起することがあるの
でAlはワイヤーボンデイング部のみに残し、他
は除去することによつて凹部として封止部との表
面積増大に寄与させるのが本発明の特徴である。
本発明のAlクラツド板を製造する方法は次の
通りである。先ず第１図に示す如きAlクラツド
Fe−Ni合金板を準備し、Al部２のうち、ワイヤ
ーボンデイングに必要な部分（第３図、第４図の
９）にレジスト膜の形成、あるいは耐薬品テープ
を貼り付けによつてマスキングし、NaOH溶液等
のアルカリ浸漬によつてマスキング部以外のAl
を除去し、そのあとレジスト又はテープを除き、
第４図の断面を有するAlクラツドFe−Ni合金テ
ープを製造することができる。
このAlクラツド板を所定形状に打抜いたリー
ドフレーム１２を用いてICパツケージを作製し
た例を第５図に示す。
実施例 予めAl巾6.3mmをその中央にクラツドした40％
Ni−Fe合金テープを用意し、その中央部に4.5mm
巾の耐薬品性テープを連続的に接着した後、20％
NaOH水溶液中で不要部のAlを溶解除去して、第
３図に示す如き、中央部4.5mm巾のAlがクラツド
され、その両側に0.9mm巾の表面粗さを大きくし
た凹部を有するAl−クラツドFe−Niテープを製
作した。
第５図は、本発明によるAl−クラツドFe−Ni
テープから打抜いて作製したリードフレームによ
るサーデイツプ型ICパツケージを示す。本発明
品によるAlクラツドテープを素材としたリード
フレームのガラス封止部の接着強度は９〜11Kgで
あり、第１図の如き従来のAl合金テープを用い
た場合の７〜８Kgに較べて約20％接着強度が向上
した。また、パツケージ後のICの高温高湿テス
トでもリーク不良率を著しく減少することができ
た。
【図面の簡単な説明】
第１図は従来のリードフレーム用Alクラツド
テープの斜視図、第２図は第１図のテープを素材
としたリードフレーム使用のICパツケージの断
面図、第３図、第４図は本発明のAlクラツド板
の実施例の断面図、第５図は本発明のAlクラツ
ド板を素材としたリードフレームで作製したIC
パツケージの断面図である。 １：Fe−Ni合金、２：Al、３：基板、４：IC
チツプ、５，１２：リードフレーム、６：封止ガ
ラス、７，９：Al、８：Alボンデンデイングワ
イヤー、１０：凹部、１１：Fe−Al層。

Claims (1)

  1. 【特許請求の範囲】 １ サーデイツプ型ICパツケージ用Alクラツド
    Fe−Ni板において、リードフレームのワイヤー
    ボンド部のみにAl層があり、その両側に凹部が
    形成されていることを特徴とするICリードフレ
    ーム用Alクラツド板。 ２ サーデイツプ型ICパツケージ用Alクラツド
    Fe−Ni板の製造法において、Fe−Ni板上のガラ
    ス封着に接する部分全面にAlをクラツドを行い
    その後、ワイヤボンデイングに必要な部分をマス
    キングしてそれ以外をエツチングによりAlを除
    去することを特徴とするAl層の両側が凹部を形
    成しているICリードフレーム用Alクラツド板の
    製造法。
JP56170396A 1981-10-23 1981-10-23 ＩＣリ−ドフレ−ム用Ａｌクラツド板及びその製造法 Granted JPS5871645A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56170396A JPS5871645A (ja) 1981-10-23 1981-10-23 ＩＣリ−ドフレ−ム用Ａｌクラツド板及びその製造法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56170396A JPS5871645A (ja) 1981-10-23 1981-10-23 ＩＣリ−ドフレ−ム用Ａｌクラツド板及びその製造法

Publications (2)

Publication Number Publication Date
JPS5871645A JPS5871645A (ja) 1983-04-28
JPS6222532B2 true JPS6222532B2 (ja) 1987-05-19

Family

ID=15904146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56170396A Granted JPS5871645A (ja) 1981-10-23 1981-10-23 ＩＣリ−ドフレ−ム用Ａｌクラツド板及びその製造法

Country Status (1)

Country Link
JP (1) JPS5871645A (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750262A (en) * 1986-05-01 1988-06-14 International Business Machines Corp. Method of fabricating a printed circuitry substrate
CN111090058A (zh) * 2019-11-22 2020-05-01 珠海格力电器股份有限公司 框架、其制备方法以及高温反相偏压试验

Also Published As

Publication number Publication date
JPS5871645A (ja) 1983-04-28

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