JPS6221145B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory backup method during a power outage, and in particular to a system for memory backup in the event of a power outage, and in particular, to reduce battery power consumption by minimizing the number of circuits that require power supply from a battery during a power outage, and to provide refresh power during a power outage. This invention relates to a memory backup system in the event of a power outage in which the address of 1 is made consecutive to the refresh address when power is applied.

2. Description of the Related Art A memory backup system is known in which data processing equipment protects information in the memory by energizing only the memory using a battery during a power outage. In such a system, if the memory used is of a dynamic type, the memory must continue to be refreshed even during a power outage. FIG. 1 shows an example of a conventional memory system that performs this operation. In FIG. 1, various memory access request signals sent from a central processing unit (CPU) 1 and channel devices 2 and 3 are sent to a memory control device 4. In this memory control device 4, a refresh request signal RS sent from a refresh control circuit 6 is used.
and the memory access request signal are sent to a priority order circuit 7, and the priority order is determined for each memory cycle.

For example, when a memory access request signal is accepted by the priority circuit 7, the address selection circuit 8 selects and outputs information from the address register 9, and when a refresh request signal is accepted, the address selection circuit 8 selects and outputs information from the address register 9. Select and output the output of. As described above, the output from the address selection circuit 8 is sent to each memory card 5, 5', 5'' as a memory address signal MS. Note that 11 is an input data register, 12 is an output data register, and Each is connected to a data bus MDS.

However, as can be seen from FIG. 1, in such a device according to the prior art, when refreshing the memory at the time of a power outage, a battery (not shown), a priority circuit 7, a refresh control circuit 6, a refresh counter, etc. 10, it is necessary to supply power to many circuits, such as the address selection circuit 8. In addition, in a system where the CPU 1 and channel device 2 and 3 interfaces operate synchronously, battery power must also be supplied to the system clock source, so even if the battery's power supply capacity is limited. Regardless, a large amount of energy will be consumed.

Furthermore, in the conventional device as described above, the address for refreshing when the power is on is interrupted due to a power outage, and the refresh address is conveniently taken over and connected to the refresh address restarted at the time of a power outage. I couldn't move.

By the way, in order to minimize the number of circuits that must be supplied with power from a battery power supply (not shown) during a power outage, as shown in Fig. 2,
It is conceivable to separate and provide only the minimum circuit necessary for refresh control during a power outage from the circuits constituting the memory control device 4 of FIG. 1, and to supply battery power to this circuit.

That is, in FIG. 2, reference numeral 20 denotes a memory refresh device during a power outage, which is supplied with power from a battery during a power outage. Memory refresh device 20 during the power outage
The system is comprised of a power failure refresh control circuit 21, a refresh signal selection circuit 22, a power failure refresh counter 23, and a memory address selection circuit 24. The memory control device 4 when energized is 4 in FIG.
It has the same configuration as . Each of the memory cards 5, 5' _, and 5'' also has the same configuration as shown in _FIG . line, _L3 is a data signal line from the memory control device 4, _L4 is a refresh signal line that performs refresh regardless of whether the power is on or in a power outage, and _L5 is a memory address signal line that sends a memory address signal regardless of whether the power is on or in a power outage. show.

Now, in FIG. 2, when the power is turned on and the power is normally supplied from the outside, the refresh signal selection circuit 22 and the memory address selection circuit 24 receive the regular refresh signal RS from the memory control device 4.
and select the memory address signal MS to line L ₄ ,
However, when a power outage occurs, a power outage detection signal indicating this is sent to the cards ₅ to 5'' through the memory refresh device 20.
For example, since it is applied to the power outage refresh control circuit 21, the power outage control signal from the power outage refresh control circuit 21 is transmitted to the refresh signal selection circuit 22 and the memory address selection circuit 2 via the line _L6 .
4, the circuits 22 and 24 are switched to the power outage mode, and the refresh signal selection circuit 22 outputs the refresh signal from the power outage refresh control circuit 21. This power failure control signal is also applied to the refresh counter 23, which starts address counting at the time of power failure and is output from the memory address selection circuit 24, thereby allowing the refresh operation to continue.

Since the refresh device 20 in the event of a power outage, which is configured with the minimum necessary circuit for refreshing as described above, is provided, the power supplied from the battery during a power outage can be suppressed to the minimum necessary amount, and Consumption is significantly lower.

Furthermore, something like the one shown in FIG. 3 is also conceivable.

In Fig. 3, the refresh device 2 during power outage
0' is composed of a refresh control circuit 21', a refresh counter 23', and drivers 30 and 31 capable of wired OR. Here, the refresh control circuit 21' corresponds to the power failure refresh control circuit 21 in FIG. 2, and the refresh counter 23' corresponds to the power failure refresh counter 23 in FIG. The drivers 30 and 31 are connected to the refresh control circuit 2.
Switching is controlled based on a switching control signal sent from 1'.

In FIG. 3, a wired-OR capable driver 3 is provided on the output side of the refresh control circuit 6 and the memory address selection circuit 8 in the memory control device 4'.
2 and 33, which are also configured to be switched during a power outage based on a switching control signal applied from the refresh control circuit 21'.

With this configuration, when the power supply is normal, the signal output from the refresh control circuit 6 and the memory address selection circuit 8 in the memory control device 4' is connected to the wired-OR driver 3.
2 and 33 through the lines L ₁ and L ₂ , and then the line
It is sent to the memories 5, 5', 5'' through L ₄ and L _5. At this time, the refresh device 20' at the time of a power outage is in a standby state because no power outage detection signal is sent, and the lines L ₇ , There is no signal output from _L8.However , when a power outage occurs and a power outage detection signal is applied to the refresh control circuit 21', a switching control signal is generated from the refresh control circuit 21'.
This connects drivers 30 and 3 via lines L ₆ and L ₉ .
1, 32, and 33. As a result, the output from the refresh control circuit 6 and the memory address selection circuit 8 is cut off, and the output from the driver 3 is turned off instead.
0 and 31 act to send the signal output from the refresh control circuit 21' and the refresh counter 23' to the memories 5, 5', 5'' via the lines _L7 and _L8.Then , this refresh device 20'
Refresh control is performed based on signals from.

Since the device shown in FIG. 3 does not use the memory address selection circuit 24 shown in FIG.
Time delays can be eliminated. Furthermore, the refresh device 20' can be configured to be detachable using a wired-or driver. Therefore, if you configure a device that does not use the refresh backup method during a power outage as shown in Figure 3, you can simply add the refresh device 20' as needed to perform backup from the system that does not perform backup. This means that it is extremely easy to migrate to a system that does this.

By the way, in the case of FIGS. 2 and 3, the refresh counter is switched during a power outage, but in general, there is no continuity in the addresses that have been executed up to that point between when the power is on and when the power is off. In other words, the address that was being used when the power was turned on is not inherited when the power is turned off. In addition, since the refresh cycle is fixed, refresh must be performed within that cycle in order to avoid destroying the memory contents when switching, so the refresh address when the power is on can be carried over even during a power outage. desirable. It is an object of the present invention to provide a memory backup system during a power outage that makes this possible.

In order to achieve the above object, the memory backup method at the time of a power outage of the present invention includes a power outage supply means capable of supplying power at the time of a power outage, a refresh address generation means for generating address information at the time of refresh, and a refresher. In the memory backup method during a power outage having a refresh control means for performing control, a power outage refresh address generation means for generating an address for a refresh during a power outage, a power outage refresh control means for controlling a refresh during a power outage, In addition to providing output signal selection means during energization and power outage, the refresh address generation means is further provided with a resettable first counter means, and a second counter that generates a carry in the refresh address generation means during power outage. A means is provided, and in the event of a power outage, the contents of the first counter that is operating when the power is on are copied to the second counter to synchronize it, and when the power is restored, the second counter is synchronized.
The present invention is characterized in that the first counter is reset by a carry signal generated from the counter, thereby achieving synchronization.

An embodiment of the present invention will be described below based on FIG. 4 and with reference to other figures. The difference in the configuration of the device shown in FIG. 4 from the device shown in FIG. 2 is that the line _L1 for sending the refresh signal RS and the line _L2 for sending the address signal are branched and connected to the refresh counter 23''. , is connected so as to feed back the carry signal of the refresh counter 23'' to the refresh counter 10'' in the memory control device 4'', and is configured so that the addresses are continuous even when the power is restored from a power failure. This is the point.

With the above configuration, at the refresh timing, the contents of the counter 10'' in the memory control device 4'' are selected by the selection circuit 8 and sent to the selection circuit 24 in the power failure refresh device 20'' via the line _S1 . It is also sent to the counter 23'', and when a power outage is detected, the contents of the counter 10'' are set to the counter 23''. The details of the loading timing of the counter 23'' are performed when the refresh signal RS is sent from the refresh control circuit 6'' via the line _S2 , and when the refresh signal RS is sent from the power failure refresh control circuit 21'' via the line _S3 . The above-mentioned setting is performed by the signal that is input.

If a power outage occurs here, the memory address selection circuit 24 of the power outage refresh device 20'' outputs the input from the power outage refresh counter 23'', and the refresh signal selection circuit 22 outputs the input from the power outage refresh control circuit 21''. Output.
At this time, the power outage refresh counter 23'' holds the refresh address when the power is on as described above, so when a refresh request is made from the power outage refresh control circuit 21'', the power outage refresh counter 23'' starts counting. Then, a refresh signal is issued to the memory via the line S ₄ and the selection circuit 24. That is, at this time, the value of the previous refresh address (at the time of energization) plus one is a continuous address.

In this way, a refresh operation can be performed during a power outage while maintaining address continuity. Even if the power is restored after the power outage is restored, the power outage refresh device 20'' continues the refresh operation.Then, the refresh counter 2
When a carry signal is generated from 3'', this carry signal resets the refresh counter 10'' of the memory controller 4'' via line _S5 . ″
This also causes the refresh control circuit 6'' to operate again. At this time, the refresh counter 10'' counts continuously with the count value of the refresh counter 23'' at the time of power outage, so that the refresh is not repeated continuously. It is possible to maintain one's sexuality.

In other words, when the power is restored, the refresh control is transferred from the power outage refresh control circuit 21'' to the refresh control circuit 6'', and thereafter the refresh address is output from the counter 10''.
At that point, the value of the refresh address changes from all "1" to all "0" to maintain refresh continuity.

As described above, the backup method of the present invention explained in FIG. ing.

As described above, in the present invention, when performing a refresh operation during a power outage, by using a simple circuit configuration, it is possible to significantly reduce battery power consumption, and even when the power is restored, the continuity is maintained.

[Brief explanation of the drawing]

FIG. 1 shows a conventional memory backup system in the event of a power outage, and FIGS. 2 and 3 show an example of a configuration provided with a memory refresh device in the event of a power outage.
FIG. 3 shows the structure of another embodiment of the present invention, and FIG. 4 shows an embodiment of the present invention in which refresh addresses are made continuous during power outage and power recovery. In the figure, 4, 4', 4'' are memory control devices, 6 is a refresh control circuit, 7 is a priority circuit, 8 is an address selection circuit, 9 is an address register, 10 is a refresh counter, 11 is an input data register, 12 is an output data register, 20, 20',
20″ is a memory refresh device during power outage, 2
1, 21', 21'' are refresh control circuits during power outage, 22 are refresh signal selection circuits, 23, 2
3', 23'' are refresh counters during power outage, 24
1 is a memory address selection circuit, and 30 to 33 are wired-OR capable drivers.

Claims (1)

[Claims] 1. In a memory backup method during a power outage, which has a power supply means during a power outage that can supply power during a power outage, a refresh address generation means that generates address information at the time of a refresh, and a refresh control means that performs refresh control, power outage refresh address generation means for generating an address for refresh during power outage; power outage refresh control means for controlling refresh during power outage; and output signal selection means for energization and power outage. The address generation means is provided with a first counter means which can be reset, and the above-mentioned refresh address generation means is provided with a second counter means which generates a carry. Synchronization is achieved by copying the contents to the second counter, and upon power restoration, the first counter is reset by a carry signal generated from the second counter. A memory backup method in the event of a power outage.