JPH04372791A - Refresh control system - Google Patents

Abstract

PURPOSE:To reduce a power consumption by optimizing a refresh execution interval at the time of a battery backup every each memory area. CONSTITUTION:A control part 5 and a memory area 1 are driven by a feeding from a basic power source 2, the control signal of the control part 5 is selected by a switching control part 8, and the writing, reading, and refresh operation of data are operated, in a normal state. The decrease of the voltage of the basic power source 2 is detected by a detecting circuit 4, and the feeding is operated from the battery 3 to the memory area 1. The control signal of an interruption-time refresh control part 6 is selected by the switching control part 8, and the refresh operation is operated independently at each memory area by the optimal refresh execution interval and execution time set in an ROM 9 of each memory area 1 by the control part 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh control method for a dynamic memory that requires refreshing during a power outage, and more particularly to a refresh control method that guarantees normal refresh operation during a power outage or when recovering from a power outage.

0002

2. Description of the Related Art As a prior art related to a power failure protection system for a dynamic memory that requires refreshing, for example, the technology described in Japanese Patent Application Laid-open No. 101691/1982 is known. In other words, in this technology, the RAM address control section used for refresh in the storage device is shared during normal times and during power outages, and the refresh control is transferred from the control section supplied with normal power to the control section supplied with battery power. or when transitioning from a battery-powered control to a normally powered control, the RA
The M address control unit can continuously refresh all areas of the memory area by taking over the refresh address. This ensures that the stored contents are retained.

0003

[Problem to be Solved by the Invention] In the above-mentioned prior art, the RAM address control section used for refresh is
Since all areas of the dynamic memory area are managed and the refresh control unit is common, refresh operations for all memory areas must be managed in common even in a storage device having a plurality of memory areas.

Therefore, if the dynamic memory used for each memory area is different, the refresh execution interval must be adjusted to the one with the shortest interval among the memory areas, and the refresh execution time must be adjusted to the one with the longest interval. must match. Therefore, there is a problem that the refresh execution interval and refresh execution time cannot be optimized for each memory area. Furthermore, when extending the refresh execution interval for the purpose of reducing power consumption, the refresh execution interval must be adjusted to the dynamic memory with the lowest value in the memory area.
There is a problem in that the effect of reducing power consumption is not noticeable.

An object of the present invention is to provide a refresh control method that reduces power consumption by optimizing the refresh execution interval for each memory area during battery backup. Another object of the invention is to
An object of the present invention is to provide a refresh control method that guarantees a normal refresh operation for each memory area during a power outage or when recovering from a power outage.

[0006]

[Means for Solving the Problem] In order to achieve the above object, the invention according to claim 1 provides a refresh control method for a storage device having a plurality of memory areas configured using a dynamic memory. a first means for performing refresh control on the memory area; a second means for performing refresh control independently for each memory area; a means for detecting an abnormality in the main power supply; and a means for detecting an abnormality in the main power supply; Accordingly, the refresh control is
The present invention is characterized by comprising means for switching from the first means to the second means backed up by a sub-power source.

According to a second aspect of the invention, the second means includes means for setting a refresh execution interval and a refresh execution time suitable for each of the memory areas.

[0008] In the invention according to claim 3, when the power supply is abnormal, the switching means switches the refresh control from the first means to the second means after detecting the end of the operation of the first means. It is characterized by

In the invention according to claim 4, the switching means changes the refresh control from the second means to the first means after detecting the completion of the operation of the second means when the main power is restored.
It is characterized by switching to the means of

[0010] In the invention described in claim 5, the refresh
a plurality of memory areas made up of memory elements each having a built-in address counter; a first means for performing refresh control on the plurality of memory areas; and a first means for performing refresh control independently for each of the memory areas. 2, and means for switching refresh control from the first means to the second means, or from the second means to the first means; It is characterized in that refresh addresses are exchanged via a refresh address counter.

[0011]

[Operation] Some dynamic memory elements require different refresh execution intervals and refresh execution times depending on their type. Therefore, when dynamic memory elements used for each memory area are different, it is desirable to perform refresh at a refresh execution interval and refresh execution time suitable for each memory area. In addition, in dynamic memory devices, the refresh execution interval values of individual memory devices vary due to variations in the manufacturing process. Therefore, in a memory area made up only of memory elements with a large value of the refresh execution interval, it is possible to extend the refresh execution interval, and therefore, it is possible to reduce power consumption. On the other hand, in a memory area made up only of memory elements with a small value of refresh execution interval, it is necessary to narrow the refresh execution interval, which increases power consumption.

According to the first aspect of the invention, when a dynamic memory of a type that generates a refresh address within a memory element is used, the RAS address counter within the memory element is After counting up, one RAS address line is refreshed, so the whole area of the memory area can be continued by simply switching the refresh control signal generation point from the control section using normal power supply to the control section using battery power supply. can be refreshed.

Further, according to the invention as claimed in claim 2, the decoded value of the counter that determines the refresh execution interval can be made variable by the setting means such as ROM for each memory area, thereby making it possible to vary the refresh execution interval. Furthermore, since the setting means adjusts the refresh execution time in the refresh control section, the refresh execution interval and refresh execution time can be set to be suitable for the dynamic memory in each memory area, and the battery backup It is possible to reduce power consumption during the time.

Further, according to the third and fourth aspects of the invention, after the refresh operation of one refresh control section is completed, the refresh operation is switched to the refresh operation of the other refresh control section, so that there is no interruption during the refresh operation. Normal refresh operation can be guaranteed without being affected.

Further, according to the invention as set forth in claim 5, when switching from the control section to the refresh control section during power outage, or when switching from the refresh control section during power outage to the control section, the memory elements are changed for each memory area. By passing the refresh address through the refresh address counter in the memory area, the refresh address of the memory area can be continuously refreshed.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, 1 is a memory area, and a storage device is configured by a plurality of memory areas. All memory areas 1 are subjected to data writing, reading, and refresh operations by the control unit 5.

This memory area 1 includes a dynamic RAM 7 which is a storage element, a power failure refresh control unit 6 that performs refresh control in the event of a power failure, control of the dynamic RAM 7 by the control unit 5, and a power failure refresh control unit 6.
The control section 8 includes a switching control section 8 that performs switching between control of the dynamic RAM 7 and a ROM 9 that stores set values for the refresh execution interval and refresh execution time of the refresh control section 6 during a power outage. In this embodiment, in order to simplify control, a type of memory is used in which a refresh address is generated inside the memory element by the CAS before RAS refresh mode, and the address is automatically incremented at each refresh cycle. There is.

In the normal state, the control section 5 and the memory area 1 are driven by power supply from the basic power supply 2, and the switching control section 8 selects the control signal of the control section 5, so that the control section 5 selects the control signal of the control section 5. Write, read, and refresh operations are performed. When the output of the basic power supply 2 is cut off due to an abnormality such as a power outage, the detection circuit 4 detects a voltage drop in the basic power supply 2, and thereby supplies power from the battery 3 to the memory area 1. When the refresh control unit 6 control signal is selected and the memory area 1
The data in the dynamic RAM 7 is retained by refreshing based on the refresh execution interval and refresh execution time set in the ROM 9.

It should be noted that the abnormality detection by the detection circuit 4 is performed before the control unit 5 becomes inoperable. That is, the time from the abnormality detection of the basic power supply 2 to the inoperability of the control unit 5 due to a voltage drop is There is sufficient margin for the data writing, reading, refreshing, and other operations performed by the control unit 5 to be completed immediately before the abnormality detection.

FIG. 2 is a diagram showing a specific configuration of the switching control section 8. As shown in FIG. As is well known, the dynamic RAM 7 uses RAS (row address strobe) and CAS (
column address strobe) signal. The switching control unit 8 receives the RAS1 and CAS1 signals from the control unit 5 and the RAS2 and CAS2 signals from the power failure refresh control unit 6.
In response to the power failure detection signal from the detection circuit 4, one of the signals of the control unit 5 and 6 is selected and sent to the dynamic RAM 7.

When the backup mode circuit 20 in the switching control section 8 receives the power failure detection signal 21 from the detection circuit 4, it sends an H (high level) signal (backup mode) to the NOR gate 23 and the power failure refresh control section 6. On the other hand, in normal times when the power failure detection signal 21 from the detection circuit 4 is not received, an L (low level) signal (normal mode) is output.

The power failure refresh control unit 6 starts operating by receiving a backup mode signal from the backup mode circuit 20, and sends RAS2 and CAS2 signals to the dynamic RAM 7. NOR gate 23 is
When the backup mode circuit 20 is outputting the backup mode signal, or when the RAS2 and CAS2 signals are output from the power failure refresh control unit 6 via the OR gate 24, the RAS1 and CA from the control unit 5
The S1 signal is inhibited from passing through AND gates 25 and 27. In other words, RAS1, CAS in normal mode
1 signal and the RAS2 and CAS2 signals in the backup mode are prevented from being supplied to the dynamic RAM 7 at the same time. As a result, the RAS1 and CAS1 signals via the AND gates 25 and 27 and the RAS2 and CAS2 signals from the power failure refresh control section 6 are combined with the OR gates 26 and 27.
The logical sum is calculated at step 8 and input to the dynamic RAM 7.

Even if the backup mode circuit 20 receives the power failure detection signal 21 from the detection circuit 4 while the RAS1 and CAS1 signals are being output from the control unit 5 via the OR gate 22, ) signal, that is, it does not shift to backup mode during normal mode operation.

FIG. 3 shows a time chart when transitioning from normal mode to backup mode. The operation of this embodiment will be explained with reference to the time chart of FIG.

When a power supply abnormality occurs in the basic power supply 2, the detection circuit 4 detects the abnormality and sets the power failure detection signal 21 to H before the voltage of the basic power supply 2 drops. At the time when the power failure detection signal 21 rises from L to H, the output of the basic power supply 2 is outputting sufficient voltage for the control unit 5 to operate, so operations such as data writing, reading, and refreshing are not performed. There is a possibility that At the time when the power failure detection signal 21 rises from L to H, the control unit 5 sends RAS1,
When the CAS1 signal is being output, that is, when an operation such as writing, reading, or refreshing data is being performed, the backup mode circuit 20 outputs an L (normal mode) signal according to the output of the OR gate 22.
Do not enter backup mode. Then, when the output of the OR gate 22 changes from H to L (control unit 5 is in a stopped state), the backup mode circuit 20 outputs H and enters the backup mode.

By shifting from the normal mode to the backup mode, the RAS2 and CAS2 signals are output from the power failure refresh control unit 6, and the memory area 1
A data retention operation is performed using a unique refresh. Here, t(pr) is the self-refresh execution interval in memory area 1. By widening the self-refresh execution interval t(pr), the number of times of self-refresh per unit time is reduced, and power consumption can be reduced. Furthermore, t(ref) is a self-refresh execution time, and power consumption can be reduced by optimizing this execution time according to the dynamic RAM of each memory area.

Note that when the value of the counter that determines the self-refresh execution interval reaches a predetermined value, R
AS2 and CAS2 signals are output, but by setting this value to a small value of the counter and resetting the counter in normal mode, the self-refresh execution time t (prs
) is within t(pr) (If this value is the final value of the counter, t(prs) is t(pr) + the time required to transition to backup mode, and t(
pr) becomes longer).

FIG. 4 shows a time chart when transitioning from backup mode to normal mode. In this time chart, two memory areas 1 (with different self-refresh execution intervals in backup mode) are shown.
A and B) illustrate a case where the transition from the backup mode to the normal mode cannot be made at the same timing. That is, while the self-refresh execution interval in the backup mode in memory area A is the same as that in FIG. 3 described above, the refresh execution interval is adjusted depending on the type of dynamic memory in memory area B. ROM9 in B
This shows a case where the value of the execution interval is set in , and there is a difference in the self-refresh execution interval of memory areas A and B. The operation of this embodiment will be described below with reference to time charts.

When the basic power supply 2 is restored and its output rises, the power failure detection signal 21 of the detection circuit 4 changes from H to L. When the power failure detection signal 21 changes from H to L, the RAS2 and CAS2 signals are not output from the power failure refresh control unit 6(A) in the memory area A, that is, the self-refresh has finished. In memory area A, backup mode circuit 20
The output of (A) changes from H to L (normal mode), and the RAS1 and CAS1 signals from the control unit 5 allow transition to normal refresh.

However, in the memory area B, when the power failure detection signal 21 changes from H to L, the RAS2 and CAS2 signals are output from the power failure refresh control unit 6 (B), that is, self-refresh is performed. is being executed, the memory area B cannot shift from the backup mode to the normal mode when the power failure detection signal 21 changes from H to L. Then, the self-refresh currently being executed is completed, and the refresh control unit 6 (
When the RAS2 and CAS2 signals from B) change from H to L, the memory area B is ready to shift to normal mode, but the RAS2 and CAS2 signals from the power failure refresh control unit 6(B) At the time when it changes from H to L, the RAS1 and CAS1 signals for normal refresh in memory area A have been output from the control unit 5, so memory area B is
, Waits for the CAS1 signal to change from H to L (guaranteeing normal refresh), and then activates the backup mode circuit 20 (
B) is changed from H to L (normal mode), thereby switching the control to the control unit 5, and the R output from the control unit 5 is changed.
It is possible to shift to normal refresh by the AS1 and CAS1 signals.

As described above, according to this embodiment, since each memory area uses a memory element having a built-in refresh address counter that operates in the CAS-before-RAS refresh mode, the refresh command from the control unit 5 and the power outage can be easily received. The refresh address counter is updated by a refresh command from the power refresh control unit 6, and each By passing the refresh address for each memory area via the refresh address counter in the memory element, it is possible to continuously refresh the refresh address of the memory area. Furthermore, according to this embodiment, when adding this function to a storage device that does not have a power failure protection function, it can be achieved by simply changing the peripheral circuit of the memory area.

FIG. 5 is a block diagram of another embodiment of the present invention. In the figure, 51 is a memory area,
As in the first embodiment, a storage device is constituted by a plurality of memory areas, and all memory areas 51 perform data writing, reading, and refresh operations by a control unit 52.

The memory area 51 outputs the logical sum of the dynamic RAM 7 which is a storage element, the power failure refresh control unit 6 that performs refresh control in the event of a power failure, the signal from the control unit 52, and the signal from the power failure refresh control unit 6. and a ROM 9 that stores set values for the refresh execution interval and refresh execution time of the power failure refresh control unit 6. That is, in the second embodiment, the switching control unit provided for each memory area in the first embodiment is made common, thereby simplifying the control logic for each memory area.

In the normal state, the control section 52, the switching control circuit 53, and the memory area 51 are driven by power supplied from the basic power supply 2, and the refresh control section 6 in the event of a power outage is driven.
Since the dynamic RAM 7 is stopped, a signal from the control unit 52 is sent to the dynamic RAM 7, thereby performing data writing, reading, and refreshing operations. When the output of the basic power supply 2 is cut off due to an abnormality such as a power outage, the detection circuit 4
detects a voltage drop in the basic power supply 2, and thereby supplies power to the switching control circuit 53 and the memory area 51 from the battery 3. The switching control circuit 53 receives a control section permission signal 55.
is turned off (L) to stop the control unit 52, and then outputs (H) the power outage refresh control unit enable signal 56, thereby operating the power outage refresh control unit 6 and setting the refresh control unit 6 in the ROM 9 of the memory area 1. Data in the dynamic RAM 7 is retained by performing refresh based on the refresh execution interval and refresh execution time.

It should be noted that, similar to the above-described embodiment, the abnormality detection by the detection circuit 4 is performed before the control section 52 becomes inoperable. The time until the operation becomes inoperable is sufficient for the control unit 52 to complete operations such as data writing, reading, and refreshing that were being performed immediately before the abnormality was detected.

FIG. 6 shows a time chart when transitioning from normal mode to backup mode in the second embodiment. The operation of the second embodiment will be explained with reference to the time chart of FIG.

When a power supply abnormality occurs in the basic power supply 2, the detection circuit 4 detects the abnormality, sets the power failure detection signal 57 to H, and sets the control section permission signal 55 to L before the voltage of the basic power supply 2 drops. Make it. At the time when the control unit permission signal 55 falls from H to L, the output of the basic power supply 2 has sufficient voltage for the control unit 52 to operate, so operations such as data writing, reading, and refreshing are not possible. It is possible that this is being done. If the control unit permission signal 55 falls from H to L, if the RAS1 and CAS1 signals are being output from the control unit 52, that is, if an operation such as data writing, reading, refreshing, etc. is being performed, the RAS
1. When the output of the CAS1 signal is completed, the control unit 52
operation stops.

After the operation of the control unit 52 is stopped, the power failure refresh control unit permission signal 56 becomes H, whereby the power failure refresh control unit 6 starts operating, and the RAS2 and CAS2 signals are output from the power failure refresh control unit 6. The data is output and the data retention operation is performed by refreshing the memory area 51 uniquely. Here, t(pr) is the self-refresh execution interval in the memory area 51. As in the first embodiment, by increasing the self-refresh execution interval t(pr), the number of self-refreshes per unit time can be reduced, and power consumption can be reduced. Also, t(ref) is
This is the self-refresh execution time, and power consumption can be reduced by optimizing this execution time according to the dynamic RAM of each memory area.

FIG. 7 shows a time chart when transitioning from the backup mode to the normal mode in the second embodiment. The operation of the second embodiment will be described below with reference to time charts.

When the basic power supply 2 is restored and its output rises, the power failure detection signal 57 of the detection circuit 4 changes from H to L, and the power failure refresh control unit permission signal 56 changes to L. Refresh control unit permission signal 56 at power outage is H
Since the RAS2 and CAS2 signals are being output from the refresh control unit 6 during a power outage, that is, the self-refresh is being executed, the RAS2,
When the output of the CAS2 signal is completed, the operation of the power failure refresh control unit 6 is stopped. Next, after the power failure refresh control unit 6 stops, the control unit permission signal 55 becomes H, and the control unit 52 starts operating.
2, the control is switched to RAS1,
The CAS1 signal enables normal refresh and data writing and reading.

As described in the first embodiment, the refresh execution interval may be different for each memory area, and as a result, the timing at which self-refresh is executed is different. After the control unit stops, the control unit permission signal 55 becomes H.
The switching control circuit 53 is operated so that.

In the above embodiment, the refresh execution interval and the refresh execution time are set in the ROM, but these may also be set by a combination of H or L level signals applied to the refresh control section during power outage. , or may be set by a switch. Furthermore, by using RAM instead of ROM, the self-refresh execution time t(re
f) may be measured and a refresh execution interval suitable for this may be written in the RAM. Furthermore, in the embodiments described above, power failure is detected on the output voltage side of the basic power supply, but it may be performed on the input voltage side.

Furthermore, although the control section is provided outside each memory area, it may also be provided within each memory area.
The RAM to be used is not the type that generates refresh addresses within the memory element as in the above embodiment, but an R
It is also possible to use a type of RAM in which a refresh address counter that is updated when the AM refresh operation ends is provided for each memory area, and a refresh address is supplied from outside.

According to the embodiment of the present invention, the refresh execution interval and refresh execution time during battery backup can be changed for each memory area, and even if the dynamic memory used for each memory area is different. Optimal refresh execution intervals and refresh execution times can be set. Furthermore, power consumption can be reduced by extending the refresh interval during battery backup, and when switching from backup mode to normal mode or from normal mode to backup mode, normal refresh and self-refresh in each memory area overlap. By switching without interruption, normal refresh operation can be guaranteed.

[0045]

As described above, according to the invention set forth in claim 1, even if different memory elements are used for each divided memory area, the optimal refresh execution interval and refresh execution time can be set. can do.

According to the second aspect of the invention, it is possible to extend the refresh execution interval for each memory area as long as the self-refresh execution time value of the memory element allows, thereby reducing power consumption during battery backup. can be reduced.

According to the third and fourth aspects of the invention, during a power outage or recovery from a power outage, normal refresh and self-refresh in each memory area can be switched without overlapping, thereby ensuring normal refresh operation. be done.

According to the fifth aspect of the invention, when switching the control section, the refresh address is transferred for each memory area via the refresh address counter in the memory element, so that the refresh address of the memory area is not changed. It can be taken over and refreshed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of a switching control section.

FIG. 3 is a time chart when transitioning from normal mode to backup mode in the first embodiment.

FIG. 4 is a time chart when transitioning from backup mode to normal mode in the first embodiment.

FIG. 5 is a block diagram of another embodiment of the present invention.

FIG. 6 is a time chart when transitioning from normal mode to backup mode in the second embodiment.

FIG. 7 is a time chart when transitioning from backup mode to normal mode in the second embodiment.

[Explanation of symbols]

1, 51 Memory area 2 Basic power supply 3 Battery 4 Detection circuit 5, 52 Control section 6 Refresh control section during power outage 7 Dynamic RAM 8 Switching control section 9 ROM 20 Backup mode circuit 53 Switching control circuit

Claims (5)

[Claims] 1. A refresh control method for a storage device having a plurality of memory areas configured using a dynamic memory, comprising: a first means for performing refresh control on the plurality of memory areas; and a refresh control method for each of the memory areas. a second means for independently performing refresh control; a means for detecting an abnormality in the main power supply; and a means for controlling the refresh from the first means in accordance with the output of the detecting means;
A refresh control method characterized by comprising: means for switching to a second means backed up by a sub-power source. 2. The refresh control method according to claim 1, wherein the second means includes means for setting a refresh execution interval and a refresh execution time suitable for each of the memory areas. 3. When the power supply is abnormal, the switching means switches the refresh control from the first means to the second means after detecting the end of the operation of the first means. 1. The refresh control method described in 1. 4. The switching means switches the refresh control from the second means to the first means after detecting completion of the operation of the second means when the main power is restored. 1. The refresh control method described in 1. 5. A plurality of memory areas each comprising a memory element having a built-in refresh address counter, a first means for performing refresh control on the plurality of memory areas, and a first means for performing refresh control on the plurality of memory areas; a second means for performing refresh control; and a second means for transferring refresh control from the first means to the second means;
means for switching from the first means to the first means, and a refresh address is transferred for each of the memory areas via a refresh address counter at the time of switching by the switching means.