JPS58169217A - Battery supporting system of data processor - Google Patents

Abstract

PURPOSE:To reduce the capacity of a battery greatly by inhibiting undesired writing to a memory chip during a failure or a commercial power source. CONSTITUTION:In case of a temporary failure of the commercial power source AC, the voltage of a DC power source 1 which is not supported by a battery is ceased. As a result, a power supply voltage is applied to none of the writing circuit 7 and reading circuit 8 of a CPU2 and read data buffer 14 and write data buffer 15, and neither writing nor reading is carried out. Then, the voltage at the connection point A between resistances 21 and 22 of the multiplexer and timing circuit 10 of the CPU2 is ceased and a transistor 20 turns off. Then, the output point C of a gate 19 is held at a low potential. Consequently, even if a timing generating circuit 17 generates a signal WE erroneously, the output signal WEM of a read data buffer 18 is ''0'' to prevent undesired writing to the memory chip 11 (nonvolatile memory) of a main storage device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (4) Technical details of the invention The present invention provides a data processing device patch V support method, %
In a data processing device that has 9 tons of volatile memo that requires refreshing, during a temporary power outage of commercial power,
The structure is configured so that only the circuit portion necessary for the write operation on the memory is utilized by the battery-supported running current sK, and undesired write operations are prohibited. The present invention relates to a data processing device/battery support system that reduces capacity.

(6) Technical background and problems Conventionally, as a measure to deal with temporary power outages of commercial power supply,
A configuration as shown in FIG. 1 was adopted.

That is, in FIG. 1, 1 is a data processing device, 2 is a central processing unit, 3 is a main storage device, 4 is an auxiliary storage device, and 5 is a DC voltage generator, which generates a DC voltage based on the commercial power supply AOK. The reference numeral 6 represents a battery, and a configuration is adopted in which the entire data processing device 1 is supported by the battery.

When the commercial power supply AC is out of power, the battery 6 is used to support the main memory 3, which is a volatile memory, until the contents of the main memory 3, which is a non-volatile memory, are transferred to the auxiliary memory tK. .

However, in this case, the battery capacity required by the battery 6 becomes large.

(0) Object and structure of the invention The present invention aims to solve the above points,
The purpose of this invention is to take care not to cause an undesired write operation to the main memory during a commercial power outage, and to ensure that the refresh operation continues, thereby reducing the capacity required for the battery. Therefore, the data processing device battery support method of the present invention includes a volatile memory chip, an address buffer, a timing buffer, a write data e-buffer, and a read data e-buffer.
A write circuit for a Uemachi storage device in a data processing device having at least a data buffer and a main storage device in which a refresh address is given and a refresh operation is performed in a state where a write enable signal is not present. , a readout circuit, a refresh instruction circuit, and a timing signal generation circuit are provided, as well as four battery-supported DC power sources and four non-battery-supported DC power sources, and the memory chip, the address buffer, and the timing signal generation circuit are provided.・The buffer, the refresh instruction circuit, and the timing signal generation circuit are connected to the battery port and the running current power supply,
The present invention is characterized in that the undesired write operation to the memory chip is prohibited and the refresh operation is performed during a power outage of the commercial power supply.

This will be explained below with reference to the drawings.

CD) Embodiment of the Invention FIG. 2 shows the configuration of a main part of an embodiment of the present invention, and FIG. 3 shows the configuration of an embodiment of the multiplexer and tinting generation circuit shown in FIG.

In FIG. 2, numerals 2, 3, 5.6 correspond to those in FIG.
■ is a battery-supported DC power supply, 7 is a write circuit, 8 is a continuous output circuit, 9 is an IJ 7 retrieval instruction circuit,
10 is a multiplexer and a timing generation circuit (hereinafter sometimes abbreviated as 'riM circuit for simplicity), 11 is a memory chip, and 12 is an address buffer, in which six access addresses for the memory chip 11 are set. 13 is a timing buffer to which timing signals including a write-enable signal are set; 14 is a write data buffer to which write data is set; 15 is a read data buffer.・Represents a turtle, which is a buffer and where read data is set. The illustrated main storage device 3 includes (1) a volatile memory chip 11t that requires refreshing;
? (-) Write operation to the memory chip 11 is prohibited in the absence of the write enable signal, and (■) will be described later in the absence of the write enable signal. Considering that the memory chip 11 is configured to be refreshed when the PALM signal tri-refresh address (RA8 address) is applied, 0.17 is sufficient.

The DC power supply DO2, which is not supported by a battery, is connected to circuits that are not involved in the refresh operation, such as the illustrated write circuit 7, continuation circuit 8, write data buffer 14, and read data buffer 15. The battery-supported running current power supply DO■ includes the illustrated refresh instruction circuit 9, TiMI circuit 10, memory
It is connected to the chip 11, address buffer 12, and tying Φ buffer 13 to ensure refresh operation.

Multiplexer and timing generation circuit (TiM circuit)
10 has a configuration as shown in FIG. Reference numeral 16 in the figure is a multiplexer that selectively extracts a given address, 17 is a timing generation circuit that generates the RA8 signal, OAS signal, WE (write enable) signal, RA8M, OA8M, WBM
are the signals set in the timing buffer 13 shown in FIG. 2, which can be thought of as the RA8 signal, OA8 signal, and WE scratch signal, respectively; 18 is an AND circuit; 19 is a NOT circuit; 20 is a transistor; 23 each represents a resistance.

Operation will be described with reference to FIGS. 2 and 83. 6 Under normal power supply conditions, the voltage at point AK shown in FIG. 3 is present, transistor 20 is turned on, and point B is at a low level. As a result, point 0 is at a high level, and the AND circuit 18 outputs the WE flaw signal as it is as a WIM signal.

When a write access is performed in this normal power supply state 1a, the write circuit 7 operates, ["Write start" becomes high level, and the timing generation circuit 1
7 issues the RA8 signal, OA8 signal and Wl signal, and the multiplexer 16 extracts the "write address". Then, the write circuit 7 converts the write data into write data.
Transfer to buffer 14.

In addition, when a read access is performed in a normal power supply state, the read circuit 8 operates, and the "q-dostart" becomes high level, and the timing generation circuit 17
are RAS signal, OA8 signal, tML, multiplexer 1
6 extracts the "read address". Then, the read circuit 8 reads read data from the read data buffer 15.

Furthermore, when a refresh operation is instructed from the refresh instruction circuit 9 in a normal power supply state, the timing generation circuit 17 issues the RA8 signal, and the multiplexer 1
6 is the refresh address t-m1lti. At this time, the main memory device 3 performs a refresh operation in the form of RA8 only refresh.

In contrast to the above, if the commercial power supply AC is temporarily interrupted, the voltage of the DC power supply DO■ shown in the faz diagram disappears. As a result, @1 circuits 7 and 8 and data buffer 1 shown in the figure
4 and 15, the write operation and read operation are not performed until the power supply voltage disappears. In this state, the voltage shown at the point in Figure 813 disappears, and the transistor 2
0Fi is turned off, and point 0 becomes a low level. At this ninth stage, due to some reason, the timing generation circuit 17
Even if W1!1 is mistakenly issued, WIM11 will be placed in the logical FO. Memory Chip II
K Unauthorized write operations are prevented from being performed.

When the refresh instruction circuit 9 issues a refresh instruction during the power outage, the timing generation circuit 17 issues the RA8 signal, and the multiplexer 16 extracts the refresh address. Even in this case, on the main storage device 3 side,
Refresh operations are performed in the form of RA8-only refresh.

(To) As described in detail, according to the present invention, when a power outage occurs, memory
It becomes possible to prevent the possibility of an undesired write operation being performed on the chip in advance, and to ensure that the refresh operation is performed correctly. This makes it possible to significantly reduce the capacity of the battery.

[Brief explanation of the drawing]

FIG. 12 shows an example of a conventional configuration, FIG. 2 shows a main part configuration of an embodiment of the present invention, and FIG. 3 shows an embodiment of the configuration of the multiplexer and timing generation circuit shown in FIG. In the figure, 2ti central processing unit, 3 main memory, 5 DC voltage generator, 6 battery, 7 write circuit, 8 read circuit, 9 refresh instruction circuit, 1G multiplexer and timing generation circuit, 11 is a memory chip,
12 is an address buffer, 13 is a timing buffer, 14 is a write data buffer, and 15 is a read buffer.
data buffer, 16 is a multiplexer, lγ is a tinging generation circuit, AO is a commercial power supply, DO■ is a battery/
An unsupported DC power supply, DO■, represents a battery supported DC power supply. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Hiroshi Mori (1 other person)

Claims (1)

[Claims] A write provided by a refresh address in the absence of a write enable signal and comprising at least a volatile memory chip, an address buffer, a timing buffer, a write data buffer, and a read data buffer. A circuit, a succession circuit, a refresh instruction circuit, and a tie-on signal generation circuit are provided, as well as a battery-supported DC power source and a non-battery-supported DC power source, which connect the memory chip and the address power supply. If the timing buffer, the refresh instruction circuit, and the tie-building signal generation circuit are connected to the battery-supported DC power source, an undesired write operation to the memory chip may occur during a commercial power outage. 9. A battery support system for a data release device, characterized in that the above-mentioned refresher operation is prohibited and the refresher operation is performed.