JPH073017U - Data processing device Battery support device - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention is designed to prevent an undesired write operation from occurring in the main memory at the time of a power failure of the commercial power supply and to allow the refresh operation to continue, thereby reducing the capacity required for the battery. The purpose is to reduce. [Structure] A memory chip, an address buffer, a timing buffer, a refresh instruction circuit, and a timing signal generation circuit are connected to a battery-supported DC power supply, and a write enable signal is generated in the event of a commercial power failure. The power supply to at least a part of the enable generation circuit is stopped.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a data processing device battery support device, particularly a data processing device having a volatile memory that requires refreshing, in the event of a temporary power failure of commercial power supply, only the circuit portion required for the refreshing operation of the memory is battery-operated. The present invention relates to a battery support device for a data processing device, which is configured so as to be utilized by a supported DC power source and is configured to prohibit an undesired write operation, thereby reducing the capacity of the battery.

[0002]

[Prior art]

 Conventionally, the configuration shown in FIG. 1 has been adopted as a measure for coping with a temporary power failure of a commercial power source. That is, in FIG. 1, 1 is a data processing device, 2 is a central processing device, 3 is a main memory device, 4 is an auxiliary memory device, 5 is a DC voltage generator, and a DC voltage is generated based on a commercial power supply AC. The reference numeral 6 denotes a battery, and the entire data processing apparatus 1 is battery-supported. Then, when the commercial power supply AC fails, the battery 6 will support it until the stored contents of the main memory 3 composed of a volatile memory are transferred to the auxiliary memory 4 which is a non-volatile memory. Has been done.

[0003]

[Problems to be solved by the device]

 However, in this case, the battery capacity required by the battery 6 becomes large. Furthermore, if an attempt is made to adopt a configuration that allows only the refresh operation during a power failure, an undesired write operation may occur for some reason.

An object of the present invention is to solve the above-mentioned problems, and to prevent an undesired write operation with respect to the main storage device at the time of a power failure of a commercial power supply, and to allow a refresh operation to continue. The purpose is to reduce the capacity required for the battery.

[0005]

[Means for Solving the Problems]

 The data processor battery support device of the present invention comprises at least a volatile memory chip, an address buffer, a timing buffer, a write data buffer, and a read data buffer, and a write enable signal. In a data processing device having a main memory device in which a refresh address and timing are given under a nonexistent state to perform a refresh operation, a write circuit, a read circuit, a refresh instruction circuit, and a timing signal for the main memory device. In addition to the preparation circuit, a battery-supported DC power supply and a battery-unsupported DC power supply are provided, and the memory chip, the address buffer, the timing buffer, the refresh instruction circuit, and the timing circuit are provided. The signal generating circuit is connected to the battery-supported DC power supply, and the power supply to at least a part of the write enable generation circuit that generates the write enable signal when the commercial power supply is interrupted is stopped. When the commercial power supply is interrupted, the write enable signal is lost to prohibit the undesired write operation to the memory chip and the refresh address and timing are given. It is characterized by being configured to be executed from time to time.

[0006]

【Example】

 2 shows the configuration of the essential parts of one embodiment of the present invention, and FIG. 3 shows the configuration of one embodiment of the multiplexer and timing generation circuit shown in FIG.

In FIG. 2, reference numerals 2, 3, 5 and 6 correspond to those in FIG. 1, DC is a DC power supply without battery support, DC is a battery-supported DC power supply, 7 is a writing circuit, Reference numeral 8 is a read circuit, 9 is a refresh instruction circuit, 10 is a multiplexer and timing generation circuit (may be abbreviated as TIM circuit hereinafter for simplicity), 11 is a memory chip, and 12 is an address buffer which is a memory. An access address for the chip 11 is set, 13 is a timing buffer for setting a timing signal including a write enable signal, and 14 is a write data buffer for writing data. Is set, and 15 is a read data buffer in which read data is set. . The main memory device 3 shown in the figure includes (i) a volatile memory chip 11 that requires refreshing, and (ii) the above memory chip under the condition that no write enable signal is present. When the write operation to the memory chip 11 is prohibited, and (iii) the RASM signal and the refresh address (RAS address) described later are given under the condition that the write enable signal does not exist, the memory chip 11 is refreshed. It may be considered configured to be performed.

The DC power supply DC that is not supported by the battery is connected to circuits such as the write circuit 7, the read circuit 8, the write data buffer 14, and the read data buffer 15 shown in FIG. . The battery-supported DC power supply DC is connected to the illustrated refresh instruction circuit 9, TIM circuit 10, memory chip 11, address buffer 12, and timing buffer 13 to ensure the refresh operation. I have to.

The multiplexer and timing generation circuit (TIM circuit) 10 has a configuration as shown in FIG. Reference numeral 16 in the figure is a multiplexer for selectively extracting an applied address, 17 is a timing generation circuit for issuing a RAS signal, a CAS signal and a WE (write enable) signal, RASM, CA SM and WEM may be considered as the RAS signal, CAS signal and WE signal, respectively, and are signals set in the timing buffer 13 shown in FIG. 2, 18 is an AND circuit, 19 is a knot circuit, 20 is a transistor, 21 to 21. Each 23 represents resistance.

The operation will be described with reference to FIGS. 2 and 3. Under normal power supply conditions, there is a voltage at point A shown in FIG. 3, transistor 20 is on and point B is at a low level. As a result, the point C is at a high level, and the AND circuit 18 outputs the WE signal as it is as a WEM signal.

When a write access is performed in this normal power supply state, the write circuit 7 operates, the “write start” becomes high level, and the timing generation circuit 17 outputs the RAS signal and the CAS signal. And the WE signal, multiplexer 16 extracts the "write address". Then, the write circuit 7 transfers the write data to the write data buffer 14.

Further, when a read access is performed in the normal power supply state, the read circuit 8 operates, “read start” becomes high level, and the timing generation circuit 17 outputs the RAS signal and the CAS signal. And the multiplexer 16 extracts the "read address". Then, the read circuit 8 reads the read data from the read data buffer 15.

Further, when the refresh operation is instructed from the refresh instruction circuit 9 in the normal power supply state, the timing generation circuit 17 issues the RAS signal, and the multiplexer 16 extracts the refresh address. At this time, the main memory 3 performs the refresh operation in the form of RAS only refresh.

On the other hand, when the commercial power supply AC temporarily fails, the voltage of the DC power supply DC shown in FIG. 2 disappears. As a result, the circuits 7 and 8 and the data buffers 14 and 15 shown in FIG. 2 have no power supply voltage, and the write operation and the read operation are not performed. In this state, the voltage at the point A shown in FIG. 3 disappears, the transistor 20 is turned off, and the point C becomes the low level. For this reason, even if the timing generation circuit 17 erroneously issues the WE signal for some reason, the WEM signal is placed at the logic "0". Therefore, the memory chip 11 is prevented from performing an undesired write operation.

When the refresh instruction circuit 9 issues a refresh instruction during the power failure, the timing generation circuit 17 issues a RAS signal and the multiplexer 16 extracts the refresh address. Even in this case, the refresh operation is performed on the main memory device 3 side in the form of RAS only refresh.

[0016]

[Effect of device]

 As described above, according to the present invention, it is possible to prevent in advance the possibility of an undesired write operation on the memory chip in the event of a power failure and to correctly perform the refresh operation. Therefore, the capacity of the battery can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a conventional configuration example.

FIG. 2 is a main part configuration of an embodiment of the present invention.

FIG. 3 shows the configuration of an embodiment of the multiplexer and timing generation circuit shown in FIG.

[Explanation of symbols]

 2 Central Processing Unit 3 Main Memory 5 DC Voltage Generator 6 Battery 7 Write Circuit 8 Readout Circuit 9 Refresh Indication Circuit 10 Multiplexer and Timing Creation Circuit 11 Memory Chip 12 Address Buffer 13 Timing Buffer 14 Write Data Buffer 15 Read data buffer 16 Multiplexer 17 Timing generation circuit

Claims (1)

[Scope of utility model registration request] 1. Refreshing under the condition that at least a volatile memory chip, an address buffer, a timing buffer, a write data buffer and a read data buffer are provided and a write enable signal is not present. In a data processing device having a main memory device in which an address and timing are applied to perform a refresh operation, a write circuit, a read circuit, a refresh instruction circuit, and a timing signal generation circuit for the main memory device are provided, and a battery is provided. A supported direct current power supply and a battery not supported direct current power supply are provided, and the memory chip, the address buffer, the timing buffer, the refresh instruction circuit, and the timing signal generation circuit have the battery support. Is connected to the DC power supply connected to the power source, and is configured to stop the power supply to at least a part of the write enable generation circuit that generates the write enable signal when the commercial power source is interrupted. Characterizing that the signal is erased to prohibit an undesired write operation to the memory chip, the refresh address and timing are given, and the refresh operation is executed even at the commercial power failure. Data processing device Battery support device.