JPS608932A - Data storing method of buffer storage device - Google Patents

Abstract

PURPOSE:To obtain a high-speed buffer storage device by setting storage data by instructing a start address and a stop address, and writing automatically storage data in a designated area extending from the start address to the stop address. CONSTITUTION:In case of executing a padding (data storage to a buffer storage device), padding data is stored in a padding data register 1 through a microprocessor bus by firmware, and a buffer address counter 2 and a padding stop address register 3 are set. Thereafter, a padding intructing bit of a transfer control register 4 is turned on. A data multiplexer 5 which has received an instruction from the register 4 selects and outputs a signal from the register 1, and supplies a strobe signal to a buffer memory circuit 7 from a timing controlling circuit 8. An address comparing circuit 6 compares inputs from the counter 2 and the register 3, stops the strobe signal from the circuit 8 when they coincide with each other, and also sends out a padding end signal to a status display register circuit 9.

Description

[Detailed description of the invention] (a) Technical field of the invention When data is transferred from one device to another.

The present invention relates to a buffer storage device for temporarily storing data, and relates to a data storage method for a buffer storage device that automatically writes stored data to a specified area of a backup memory.

(b) Background of the technology Since the input/output devices in a computer system are different from the central processing unit, etc., it is important to operate these different types of devices within a computer system without constraining each other as much as possible to improve system efficiency. The input/output control method for improving the performance is one of the key points in configuring a computer system.

Separate input/output control from the central processing unit as much as possible and make it independent, and create an input/output control unit for each input/output device and operate them in parallel to buffer the imbalance in operating speed between the central processing unit and input/output devices. System efficiency can be further improved by adjusting the storage device or the like.

As the use of electronic computer systems becomes more sophisticated and complex, the requirements for improving the efficiency of the entire system become more severe, and accordingly, there is a demand for more efficient control of buffer storage devices commensurate with the improvement in system efficiency.

(C) Prior Art and Problems Conventionally, data is stored in a buffer storage device (hereinafter referred to as padding) by a method in which firmware writes directly to the buffer storage device, but the number of bytes to be padded is If is large, the disadvantage is that it is not efficient because it takes too much time.

(d) Object of the Invention The object of the present invention is to provide a novel padding method for a buffer storage device that eliminates the above-mentioned drawbacks, and in particular, a means for instructing start/stop addresses and padding data for padding in a buffer storage device. An object of the present invention is to realize a padding method for a buffer storage device, which reduces the time required for padding and improves the processing capacity of the buffer storage device by performing padding with hardware.

(e) Structure of the Invention The present invention provides means for instructing a start address, means for instructing a stop address, in a buffer storage device for temporarily storing data when transferring data from one device to another. By providing means for setting padding data and automatically writing the padding data into a specified area from the start address to the stop address of the buffer storage device, the time required for padding can be reduced and the processing capacity of the buffer storage device can be reduced. This can be achieved by a padding method for a buffer storage device, which is characterized by improved performance.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 1 shows an embodiment of a method for padding a buffer storage device according to the present invention.

In the figure, 1 is a padding data register, 2 is a buffer address counter, 3 is a padding stop address register, 4 is a transfer control register, 5 is a data multiplexer, 6 is an address comparison circuit, 7 is a buffer memory circuit, and 8 is a timing control circuit. , 9 indicate status display register circuits, respectively.

This embodiment is a part of a magnetic disk control circuit, and the buffer memory circuit 7 has a capacity to store data for one trunk of a magnetic disk.

The configuration of this embodiment includes a padding data register 1 that stores padding data instructed by firmware (not shown), and a buffer address that is initialized by instructions of the firmware (not shown) and counts the address of the buffer memory circuit 7. Counter 2, firmware (
Padding stop address register 3 that stores the padding stop address indicated by (not shown)
, a padding instruction signal is sent to the data multiplexer 5 in response to a padding start instruction from firmware (not shown).
Transfer control register 4 outputs to timing control circuit 8
, a data multiplexer 5 that selects either information from another device (not shown) or information in the padding data register 1 depending on the presence or absence of a padding instruction signal from the transfer control register 4, and outputs the data to the buffer memory circuit 7. , an address comparison circuit 6 that compares the input from the buffer address counter 2 and the input from the padding stop address register 3 and outputs the comparison result to the timing control circuit 8, and information and padding from other devices (not shown). The input signals from the buffer memory circuit 7 that stores data, the address comparison circuit 6, and the transfer control register 4 start supplying a strobe signal instructing the start of writing data to the buffer memory circuit 7, and when the supply of the strobe signal is stopped, a padding end signal is sent. The timing control circuit 8 outputs the signal to the status display register circuit 9, and the status display register circuit 9 stores the padding end signal in a readable state from firmware (not shown).

In the case of normal data transfer in this embodiment, the data multiplexer 5 outputs a signal from the data bus as write data to the backup memory circuit 7.

The address of the buffer memory circuit 7 is supplied by the buffer address counter 2. The buffer address counter 2 has an initial value set by a signal from the microprocessor bus, that is, by firmware (not shown), and is automatically updated every time one byte is transferred.

If padding is to be performed, the firmware (not shown) sends the padding data register 1. Buffer address counter 2. After setting the padding stop address register 3, turn on the padding instruction pin of the transfer control register 4.

Note that the initial setting value of the buffer address counter 2 becomes the padding start address.

The data multiplexer 5 that receives the padding instruction signal from the transfer control register 4 selects and outputs the output signal from the padding data register 1, that is, the padding data, as write data to the buffer memory circuit 7, and outputs the output signal from the timing control circuit 8. Supply of a strobe signal to the buffer memory circuit 7 for writing data to the buffer memory circuit 7 is started.

The address comparison circuit 6 compares the buffer address input from the buffer address counter 2 with the padder stop address input from the padding stop address register 3, and outputs the comparison result to the timing control circuit 8. When the buffer address and the padding stop address match, the timing control circuit 8 stops supplying the strobe signal to the buffer memory circuit 7 and sends a padding end signal to the status display register circuit 9 that can be read from firmware (not shown). Send.

As described above, in this embodiment, after instructing the firmware to start padding, the firmware (not shown) only needs to read the status display register 9 and detect the reception of the padding end signal, and perform other processing while the padding is being executed. It is also possible to do so. Further, a padding data register 1 is provided to set the padding data to an arbitrary value, but if the padding data can be a specific value, the padding data register 1 is not necessary and the data pattern can be input directly to the data multiplexer 5. In this case, there is an effect that the number of circuits can be reduced.

(g) Effects of the Invention As described above, according to the present invention, padding can be performed quickly in any area of a buffer storage device, thereby reducing the time required for padding and improving the processing capacity of the buffer storage device. .

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a method for padding a buffer storage device according to the present invention. In the figure, 1 is a padding data register, 2 is a buffer address counter, 3 is a padding stop address register, 4 is a transfer control register, 5 is a data multiplexer, 6 is an address comparison circuit, 7 is a buffer memory circuit, and 8 is a timing control circuit. , 9 indicate the status display register circuit 9 -175

Claims (1)

[Claims] When transferring data from one device to another. A buffer storage device for temporarily storing data, provided with means for instructing a start address, means for instructing a stop address, and means for setting stored data,
A data storage method for a buffer storage device, characterized in that the storage data is automatically written into a designated area from the start address to the stop address of the buffer storage device.