JPS6041163A - Synchronous operating method of duplex microprocessor - Google Patents
Synchronous operating method of duplex microprocessorInfo
- Publication number
- JPS6041163A JPS6041163A JP58149344A JP14934483A JPS6041163A JP S6041163 A JPS6041163 A JP S6041163A JP 58149344 A JP58149344 A JP 58149344A JP 14934483 A JP14934483 A JP 14934483A JP S6041163 A JPS6041163 A JP S6041163A
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- microprocessor
- output
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Abstract
Description
【発明の詳細な説明】
本発明は２重化マイクロプロセッザの同期運転方式に関
し、特に２重化マイクロプロセッサを用いた電子交換機
や電子計算機等の運転方式における２重化マイクロプロ
セッサの同期運転方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous operation method of a duplex microprocessor, and particularly to a synchronous operation method of a duplex microprocessor in an operation system of an electronic exchange, an electronic computer, etc. using a duplex microprocessor. Regarding.
従来、この種の装置におけるマイクロプロセッサの２重
化運転は、両糸のメモリへの同時書込や共通メモリの使
用によシ行われている。しかるにこの２Ｍ化運転ではマ
イクロプロセッサ内部の制御ができないので、同期運転
することが困難であるという問題があった。Conventionally, the redundant operation of the microprocessor in this type of device has been achieved by writing to the memories of both threads simultaneously or by using a common memory. However, in this 2M operation, there was a problem in that it was difficult to perform synchronous operation because the microprocessor could not be controlled internally.
本発明の目的は、外部からの制御信号を同期化して両マ
イクロプロセッサに供給することによって入出力母線の
同期入出力制御を行いまた共通のクロック回路を用いる
ことにより上記問題点を解決し、両マイクロプロセッサ
の同期運転を可能にした２重化マイクロプロセッサの同
期運転方式を提供することにある。An object of the present invention is to perform synchronized input/output control of input/output buses by synchronizing external control signals and supplying them to both microprocessors, and to solve the above problems by using a common clock circuit. It is an object of the present invention to provide a synchronous operation method for duplicated microprocessors that enables synchronous operation of microprocessors.
本発明によれば、２重化されたマイクロプロセッサおよ
びメモリと、該マイクロプロセッサに共通にクロックを
供給するクロック回路と、入出力装置と、前記マイクロ
プロセッサ、メモリおよび入出力装置を接続する入出力
母線とからなる２重化マイクロプロセッサを用いた装置
の運転方式において、外部からの制御信号を同期化して
前記マイクロプロセッサに供給することにより前記入出
力母線の同期入出力制御を行う手段を備えることを特徴
とする２重化マイクロプロセッサの同期運転方式が得ら
れる。According to the present invention, a duplicated microprocessor and memory, a clock circuit that commonly supplies a clock to the microprocessor, an input/output device, and an input/output device that connects the microprocessor, memory, and input/output device. In an operating method of an apparatus using a duplex microprocessor comprising a bus bar, the apparatus is provided with means for synchronizing input/output control of the input/output bus bar by synchronizing an external control signal and supplying the same to the microprocessor. A synchronous operation system for dual microprocessors is obtained, which is characterized by the following.
次に図面を参照して本発明について説明する。Next, the present invention will be explained with reference to the drawings.
図は本発明の２重化マイクロプロセッサの同期運転方式
の一実施例を示すブロック図である。同図において、２
重化マイクロブ四セッサを用いた装置はクロック回路１
と、２亘化された１テツプマイクロプロセツサ（以下単
にマイクロプロセッサ）２．２’およびメモ！Ｊ４，４
’と、入出力母線同期制御回路３と、入出力装置５と、
外部信号同期制御回路６と、入出力母線７，７′および
８，８′とからなる。クロック回路１はクロック供給線
１０によシマイクロプロセッサ２，２′と接続され、マ
イクロプロセッサ２，２′はそれぞれ入出力母線７．７
′と接続され、入出力母線７，７′と入出力母線８，８
′はそれぞれ入出力母線同期制御回路３を介して接続さ
れる。また入出力母線８，８′にはそれぞれメモ！ｊ４
，４’および入出力装置５が接続され、外部信号制御線
１３から入力されマイクロプロセッサを制御（リセット
、現用予備切替等）する外部制御信号を同期化して同期
制御信号を出力する外部信号同期制御回路６はマイクロ
プロセッサ制御線１１によシマイクロプロセッサ２，２
′と接続されるとともに障害通報線１２によシ入出力母
線同期制御回路３と接続される。東に入出力母線同期制
御回路３は入出力母線７，８問および入出力母線７／、
８／間にそれぞれ介在するゲート回路３０および３０′
と、入出力母線７．７’上の出力情報を照合する出力情
報照合回路３１と、入出力母線８，８′上の入力情報を
照合する入力情報照合回路３２と、出力情報照合回路３
１．入力情報照合回路３２の照合結果に基つきゲート制
御線３４゜３４′を介してそれぞれゲート回路３０．３
０’を制御し且つ障害通報線１２を介して外部信号同期
制御回路６に障害を通報する同期回路３３とからなる。The figure is a block diagram showing an embodiment of the synchronous operation method of the dual microprocessors of the present invention. In the same figure, 2
The clock circuit 1 of the device using the multiplexed microb four processors is
2.2' and a memo! J4,4
', an input/output bus synchronization control circuit 3, an input/output device 5,
It consists of an external signal synchronization control circuit 6 and input/output buses 7, 7' and 8, 8'. The clock circuit 1 is connected to microprocessors 2 and 2' by a clock supply line 10, and the microprocessors 2 and 2' are connected to input/output buses 7 and 7, respectively.
', input/output buses 7, 7' and input/output buses 8, 8
' are connected via the input/output bus synchronization control circuit 3, respectively. Also, take notes on each of the input/output buses 8 and 8'! j4
, 4' and the input/output device 5 are connected, and an external signal synchronous control that synchronizes external control signals that are input from the external signal control line 13 and controls the microprocessor (reset, active/standby switching, etc.) and outputs a synchronous control signal. The circuit 6 is connected to the microprocessor 2, 2 via the microprocessor control line 11.
' and is also connected to the input/output bus synchronization control circuit 3 through the fault reporting line 12. The input/output bus synchronous control circuit 3 on the east includes the input/output buses 7 and 8 and the input/output bus 7/,
8/gate circuits 30 and 30' respectively interposed between
, an output information matching circuit 31 that matches the output information on the input/output buses 7, 7', an input information matching circuit 32 that matches the input information on the input/output buses 8, 8', and an output information matching circuit 3.
1. Based on the verification result of the input information verification circuit 32, each gate circuit 30.
0' and notifies the external signal synchronization control circuit 6 of a failure via the failure notification line 12.
続いて本実施例の動作について説明する。マイクロプロ
セッサ２，２′はクロック回路１からクロック供給線１
０を介して受信するクロックと外部信号同期制御回路６
からマイクロプロセッサ制御線１１を介して受信する同
期制御信号によ如動作し、入出力母線’１．７’ 、ゲ
ート回路３０ 、３０’ 、入出力母線８，８′を介し
てメモｌＪ４，４’および入出力装置５をアクセスする
。すなわち入出力母線７．７′から情報が出力される場
合は、出力情報照合回路３１は該入出力母線７，７′上
のデータ、アドレス、制御信号の情報の照合を行いこの
照合結果が一致すると同期回路３３を動作させるので、
同期回路３３はゲート制御線３４．３４’を介してゲー
ト回路３０．３０’の順方向（入出力母線７，７′から
入出力器＆１８，８’への方向）のゲートをオンにする
。従って入出力母線７，７′上の前記情報はそれぞれ入
出力器６８．８’を介してメモ！ｊ４，４’ｔたは入出
力装置５に出力される。苔だメモリ４，４′または入出
力装置５から情報が入力される場合は、入力情報照合回
路３２が入出力母線８，８′上の該情報の照合を行いこ
の照合結果が一致すると同様に同期回路３３を動作させ
る。同期回路３３はゲート制御線３４．３４’を介して
ゲート回路３０ 、３０’の逆方向（入出力母線８，８
′から入出力母線７，７′への方向）のダートをオンに
するので、入出力母線８，８′上の前記情報はマイクロ
プロセッサ２，２′に取り込まれる。更に上記照合結果
が不一致の場合や一定時間内に出力、入力情報照合回路
３１．３２に情報が入力されない場合は、同期回路３３
は障害通報線１２を介して外部信号同期制御回路６に障
害情報を通報する。外部信号同期制御回路６は該障害情
報によシ同期制御情報をマイクロプロセッサ制御練具１
を介してマイクロプロセッサ２゜２′へ送るので現用予
備の切替えが行われる。従って本実施例によれば、入出
力母線７，７’ 、 ８，８’上の情報の障害を早期検
出して所要の処理を行うことができる。Next, the operation of this embodiment will be explained. The microprocessors 2 and 2' are connected to the clock supply line 1 from the clock circuit 1.
Clock and external signal synchronization control circuit 6 received via 0
It operates according to the synchronization control signal received from the microprocessor control line 11 through the input/output bus ``1.7'', gate circuits 30, 30', and input/output buses 8, 8' to memory lJ4, 4. ' and access the input/output device 5. In other words, when information is output from the input/output buses 7, 7', the output information matching circuit 31 checks the information on the data, addresses, and control signals on the input/output buses 7, 7', and determines that the matching results match. Then, the synchronization circuit 33 is activated, so
The synchronization circuit 33 turns on the gate in the forward direction (from the input/output buses 7, 7' to the input/output devices &18, 8') of the gate circuit 30, 30' via the gate control line 34, 34'. Therefore, the information on the input/output buses 7, 7' is memorized via the input/output devices 68, 8', respectively. j4,4't or is output to the input/output device 5. When information is input from the moss memories 4, 4' or the input/output device 5, the input information matching circuit 32 matches the information on the input/output buses 8, 8', and if the matching results match, the same applies. The synchronous circuit 33 is operated. The synchronous circuit 33 connects the gate circuits 30 and 30' in the opposite direction (input/output buses 8 and 8) via gate control lines 34 and 34'.
' in the direction from the input/output busses 7, 7'), the information on the input/output buses 8, 8' is taken into the microprocessor 2, 2'. Furthermore, if the above matching results do not match or if no information is input to the output and input information matching circuits 31 and 32 within a certain period of time, the synchronization circuit 33
notifies the external signal synchronization control circuit 6 of failure information via the failure notification line 12. The external signal synchronization control circuit 6 transmits synchronization control information to the microprocessor control tool 1 based on the failure information.
Since the data is sent to the microprocessor 2.2' through the 2.sup.2', switching between the active and standby data is performed. Therefore, according to this embodiment, failures in information on the input/output buses 7, 7', 8, 8' can be detected early and necessary processing can be performed.
以上の説明によシ明らかなように本発明の２重化マイク
ロプロセッサの同期運転方式によれば、外部からの制御
信号を同期化してマイクロプロセッサに供給することに
よって入出力母線の同期入出力制御を行うので、２重化
マイクロプロセッサの同期運転が可能になるという効果
が生じる。As is clear from the above explanation, according to the synchronous operation method of the duplex microprocessor of the present invention, synchronous input/output control of the input/output buses is performed by synchronizing control signals from the outside and supplying them to the microprocessor. Therefore, there is an effect that synchronous operation of the duplicated microprocessors becomes possible.
図は本発明の２重化マイクロプロセッサの同期運転方式
の一実施例を示すブロック図である。
図において、１・・・・・・クロック回路、２，２’・
・・・・・１チツプマイクロプロセツサ、３・・・・・
・入出力母線同期制御回路、４，４’・・・・・・メモ
１ハ ５・・・・・・入出力装置、６・・・・・・外部
信号同期制御回路、７．７’、８゜８′・・・・・・入
出力母線、１０・・・・・・クロック供給線、１１・・
・・・・マイクロプロセッサ制御線、１２・・・・・・
障害通報線、１３・・・・・・外部信号制御ｉｌ、３０
．３０’・・・・・・ゲート回路、３１・・・・・・出
力情報照合回路、３２・・・・・・入力情報照合回路、
３３・・・・・・同期回路、３４．３４’・・・・・・
ゲート制御線。The figure is a block diagram showing an embodiment of the synchronous operation method of the dual microprocessors of the present invention. In the figure, 1... clock circuit, 2, 2'...
...1 chip microprocessor, 3...
- Input/output bus synchronization control circuit, 4, 4'... Memo 1c 5... Input/output device, 6... External signal synchronization control circuit, 7.7', 8゜8'...Input/output bus line, 10...Clock supply line, 11...
...Microprocessor control line, 12...
Fault reporting line, 13...External signal control il, 30
．． 30'...Gate circuit, 31...Output information verification circuit, 32...Input information verification circuit,
33...Synchronous circuit, 34.34'...
gate control line.
Claims (1)
イクロプロセッサに共通にクロックを供給するクロック
回路と、入出力装置と、前記マイクロプロセッサ、メモ
リおよび入出力装置を接続する入出力母線とからなる２
重化マイクロブロセッザを用いた装置の運転方式におい
て、外部からの制御信号を同期化して前記マイクロプロ
セッサに供給することによシ前記入出力母線の同期入出
力制御を行う手段を備えることを特徴とする２重化マイ
クロプロセッサの同期運転方式。A 2M microprocessor and memory, a clock circuit that commonly supplies a clock to the microprocessor, an input/output device, and an input/output bus connecting the microprocessor, memory, and input/output device.
In an operating method of a device using a multi-layered microprocessor, the method includes means for synchronizing input/output control of the input/output bus by synchronizing a control signal from an external source and supplying the synchronized control signal to the microprocessor. Features a synchronized operation method of dual microprocessors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58149344A JPH063587B2 (en) | 1983-08-16 | 1983-08-16 | Synchronous operation method of dual microprocessor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58149344A JPH063587B2 (en) | 1983-08-16 | 1983-08-16 | Synchronous operation method of dual microprocessor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6041163A true JPS6041163A (en) | 1985-03-04 |
| JPH063587B2 JPH063587B2 (en) | 1994-01-12 |
Family
ID=15473061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58149344A Expired - Lifetime JPH063587B2 (en) | 1983-08-16 | 1983-08-16 | Synchronous operation method of dual microprocessor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH063587B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01154242A (en) * | 1987-09-04 | 1989-06-16 | Digital Equip Corp <Dec> | Double-zone failure-proof computer system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5635254A (en) * | 1979-08-29 | 1981-04-07 | Yokogawa Hokushin Electric Corp | Processor back-up system |
| JPS56123042A (en) * | 1980-03-03 | 1981-09-26 | Fujitsu Ltd | Fault detection and recovery system in processor synchronizing operation |
-
1983
- 1983-08-16 JP JP58149344A patent/JPH063587B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5635254A (en) * | 1979-08-29 | 1981-04-07 | Yokogawa Hokushin Electric Corp | Processor back-up system |
| JPS56123042A (en) * | 1980-03-03 | 1981-09-26 | Fujitsu Ltd | Fault detection and recovery system in processor synchronizing operation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01154242A (en) * | 1987-09-04 | 1989-06-16 | Digital Equip Corp <Dec> | Double-zone failure-proof computer system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH063587B2 (en) | 1994-01-12 |
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