JPH01116801A - Dual system switching method - Google Patents

Abstract

PURPOSE:To always check the soundness of a stand-by system by accessing a register provided on the bus receiver of an input/output part or the bus driver of a central processing unit part with the central processing unit part of the stand-by system disconnected from the input/output part. CONSTITUTION:In a bus receiver 8 of the stand-by system disconnected from an input/output bus 15 of an input/output part 3 by a dual system switching command signal, data is written in a register 21 for self-diagnosis from a CPU part 2 through a control signal line 24b, and data in the same address is read through a control signal line 24a thereafter. The CPU part 2 of the stand-by system always accesses the bus receiver 8 up to the last stage from a bus driver 7 by this processing and data outputted from the CPU part 2 is compared with this data, which is read back by the next processing after being temporarily stored in the register 21 for self-diagnosis, to always check the soundness of the stand-by system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual system switching system for a control device constituting a standby redundant system.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional dual system switching system disclosed in, for example, Japanese Unexamined Patent Publication No. 61-235901.
2 is the CPU section of the B system which is duplicated with the CPtJ section 1 of the A system to form a standby redundant system, and 3 is the input/output accessed by the CPU sections 1 and 2 of the A system and B system. 4 is a dual system switching command unit that manages the A system and B system, 5 is a path driver that links the CPU unit 1 of the A system and the input/output unit 3, 6 is a similar bus receiver, and 7° and 8 are A B-system path driver and receiver, 9 is an input card, and 10 is an output card.

In addition, 11 is a signal from the dual system switching command section 4 to c of the A system and B system.
13.14 A signal for specifying the active system or standby system mode for the PU units 1 and 2; 12 is a switching signal for the active system or standby system from the dual system switching command unit 4 to the bus receiver; 13.14
are the A-system and B-system CPU cards, 15 is the path 1 of the input/output section, and 16 and 17 are failure state signals indicating the self-diagnosis results of the A-system and B-system CPU sections 1.2, respectively.

Next, the operation will be explained. In Figure 2, A system, B system
The 020 units 1 and 2 of the systems have the same function, are equal as systems, and are duplexed to form a standby redundant system, with one of the systems always being the active system and the other system being the standby system.

Operation/standby instructions are given by dual system mode signals 11 and 12 from the dual system switching command unit 4.

The following explanation will be given assuming that system A is the active system and system B is the standby system. The 020 unit 1 of the A system learns from the signal 11 from the dual system switching command unit 4 that its own system is the active system, and performs processing operations as the active system.

At this time, an active system command signal is simultaneously transmitted from the dual system switching command section 4 to the bus receiver 6, and the A system 020 section 1 is linked to the input/output section 3 via the bus driver 5 and bus receiver 6.

At the same time, a standby system command signal is transmitted from the dual system switching command section 4 to the standby system CPU section 2 and the standby system bus receiver 8. As a result, the CPU section 2 of the B system performs processing operations as a standby system, and the bus receiver 8 is prohibited from accessing the expansion bus of the input/output section 3 by the standby system command signal. 020 part 1 is input/output card 9, 10
When accessing, there will be no interference with the input/output section 3.

A block diagram of the bus receiver 6 in a conventional configuration is shown in FIG. The active system will open the gate of the 3-state buffer, and the standby system will close it. That is, the dual system switching command from the dual system switching command unit 4 is input to the 3-state buffers 198 to 19d, respectively, and the 3-state buffer 19a is inputted to the buffer 18a and the C via the address bus.
The operational command from the PU 1 is transmitted to the input/output bus 15.

:3xchi) Buffer 19b is buffer 18b.

The 3-state buffer 19c transmits data to the input/output bus 15 via the control signal bus, and the 3-state buffer 19c transmits data from the 020 section 1 via the buffer 18C and the data bus to the input/output bus 15.
to be transmitted.

On the other hand, the 3-state buffer 19d transmits data from the input/output lot 15 to the 020 unit 1 via the buffer 18d and the data bus.

Here, the standby system processing of the B system CPU section 2 refers to the data for bumpless switching of the output without causing instantaneous output fluctuations when switching from the standby system to the active system by the dual system switching command section 4. These include tracking processing, etc., and self-diagnosis processing as a standby system (the circuit for tracking data is not shown).

It also means a system bus that connects the CPU section and input/output, such as IBE 796 HAS (Intel Multipath).

[Problem that the invention seeks to solve]

Since the conventional dual system switching system is configured as described above, the signals for judgment in the dual system switching command unit 4 are that the A system and B system of the failure status signal 16.17 are normal. This is a status signal indicating whether there is an internal failure factor.

This is based on the results of self-diagnosis of A and B systems. That is, if an abnormality occurs in the A system according to the self-diagnosis result, the system is switched to the B system, but at this time, it is necessary to confirm that the B system is healthy.

In conventional control devices, the health of system B is confirmed by executing a diagnosis of the CPU section, but since the active system and standby system are designated by a signal from the dual system switching command unit, the standby system There was a problem in that it was not possible to determine whether or not the bus driver and bus receiver were in operation, making it impossible to confirm their health.

This invention was made to solve the above-mentioned problems, and aims to provide a highly reliable dual system switching system by diagnosing the standby system bus driver and receiver section. .

[Means for solving problems]

The dual system switching method according to the present invention provides a register for self-diagnosis in the bus receiver section or the bus driver section provided in the input/output section that is accessed from the central processing unit of the active system and the standby system. This register can be accessed by the standby central processing unit even when the standby central processing unit is separated from the input/output unit by a command from the switching command unit.

[For production]

In this invention, when the standby central processing unit is separated from the input/output unit, it is possible to maintain the health of the standby system by accessing the register installed in the bus receiver of the input/output unit or the bus driver in the central processing unit. It is possible to check the sex at any time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 22 is an address bus usually consisting of 16 to 20 signal lines, 23 is a bidirectional data bus usually consisting of 16 signal lines, and 24 is a control signal bus consisting of read or write commands.

Buffer 18a between address bus 22 and input/output bus 15
and 3-state buffer 19a are connected, and buffers 18b and 3-state buffer 19a are connected between control signal bus 24 and input/output bus 15.
A state buffer 19b is connected, and a buffer 18c and a 3-state bus 19c are connected between the data bus 23 and the input/output bus 15. A 3-state buffer 19d, a bidirectional data bus 23a, and a buffer 19c are connected between the data bus 23 and the input/output bus 15. 18d is connected. 21 is a register for self-diagnosis, and the address bus 23 is an address decoder 20.
and a buffer 18e.

It is connected to the bidirectional data bus via 18f, and control signal lines 2Ja for read, write, etc.
24b.

Next, the operation will be explained. In normal standby redundant duplexing, the circuit shown in FIG. 1 is applied to the bus receiver 6.8 in the configuration shown in FIG. □In this state, A system CPU
Part 1 is accessing the input/output cards 9 and 10 via the bus driver 5 and bus receiver 6, and during this time the standby system is
Processing is performed to follow internal status signals of system A sent from the system via another route (not shown).

At the same time, self-diagnosis processing is performed by read/write access to the peripheral memory of CPU section 1, section 0, etc., and by a watchdog timer, etc., which CPtJ itself has as nodeware.

In parallel with the above processing, the CPU section 1 accesses the register 21 of the bus receiver 6. Although this register 21 is accessed by the memory mapped card 10 (input/output) like other input/output cards, it is manually set in advance by the address decoder section 20 so that it does not match the address of the input/output card.

Due to the dual system switching command signal, the input/output lot 1 of the input/output section 3
In the standby bus receiver 8 separated from C.
After data is written from the PU unit 2 to the self-diagnosis register 21 via the control signal line 24b, data at the same address is subsequently read via the control signal line 24a.

Through this process, the standby CPU section 2 is connected to the bus driver 7.
CP to the final stage of bus receiver 8.
The health of the standby system is checked by comparing the data output from the U unit 2 with the data read back in the next process after this data is once stored in the self-diagnosis register 21.

If an error is detected by this self-diagnosis,
By issuing the B system (standby system) failure status signal 17 in FIG. 2 to the dual system switching command unit 4, maintenance can be performed before a failure occurs in the active system. In duplication and single input/output sections, even the bus receiver is often duplicated as shown in FIG. 2, so this embodiment has been described with reference to providing a diagnostic register in the bus receiver.

In systems where economic efficiency is important, the bus driver section is duplicated, but the bus receiver section is sometimes made single.

In this case, it goes without saying that the same effect as this embodiment can be obtained by providing a diagnostic register in the bus driver section.

〔Effect of the invention〕

As described above, according to the present invention, the standby central processing unit is separated from the input section by a command from the dual switching command section to set the register for self-diagnosis in the standby bus receiver or bus driver. Since the central processing unit is configured to be able to access the resist even in the case of a standby system, the self-diagnosis area of the standby system reaches approximately 100 pixels, which has the effect of increasing reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bus receiver in a dual system switching system according to an embodiment of the present invention, FIG. 2 is a block diagram showing the overall configuration of this invention and a conventional dual system switching system, and FIG. FIG. 2 is a block diagram of a bus receiver unit in a conventional dual system switching system. 1 is an A-system CPU section, 2 is a B-system CPU section, 3 is an input/output section, 5.7 is a path driver, 6 and 8 are bus receivers, 21
is a register. Note that the same reference numerals in the figures indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation Figure 2

Claims (1)

[Claims] A central processing unit that is duplicated, one of which operates as an active system and the other as a standby system, is connected as a common element to the central processing units of both the active system and the standby system, and a signal In a control device having an input/output unit that performs input/output, in a bus driver or bus receiver unit that connects the central processing unit units of both systems and the input/output unit, the standby central processing unit unit performs input/output operations. A dual system switching system characterized in that a register for self-diagnosis is provided for performing self-diagnosis of the standby system by accessing it in a state separated from the output section.