JPH01258158A - Trouble diagnosing circuit for interface ic - Google Patents

Abstract

PURPOSE:To improve the reliability of an input/output interface by providing a bidirectional bus driver which connects I/O ports to each other and a buffer which disconnects an external device and an interface IC from each other to check the interface IC while holding the signal to the external device. CONSTITUTION:When an interface IC 2 will be checked, sending of a clock to a latch 5 from which data is sent out is stopped and the signal to the external device is held on the output side of the latch 5, and the address for check of the interface IC 2 is assigned to a control register 15 of the interface IC 2 and input/output ports 16 and 17, and a bidirectional buffer 4 is operated, and data is exchanged between input/output ports 16 and 17. Thus, the signal to the external device is held by the latch and does not disappear when the interface IC 2 is checked, and the malfunction of the external device due to disappearance of the signal at the time of check is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output interface for a robot controller or the like, and particularly to a failure diagnosis circuit for an input/output interface IC.

[Conventional technology]

To deal with failures in the input/output interface IC, it is preferable to configure the interface IC in a duplex configuration, but this increases costs, so conventionally
As described in Japanese Patent No. 66115, a check circuit for diagnosing failure is provided separately from the interface IC.

[Problem to be solved by the invention]

When the check circuit according to the prior art detects an abnormality in the interface IC, the signal to be sent to the external device is lost, causing the external device to malfunction. This is because no consideration is given to retaining the signal that should be sent to the external device when an abnormality is detected in the interface IC.

SUMMARY OF THE INVENTION An object of the present invention is to provide a failure diagnosis circuit for an input/output interface IC that checks for abnormalities in the interface IC while retaining signals sent from an external device.

[Failure to solve the problem]

The above purpose is to stop sending the clock to the latch that is sending out data when checking the interface IC, hold the signal to the external device on the output side of the latch, and connect the control register of the interface IC and the I/O. C
This is achieved by assigning a check address of an interface IC to a port, operating a bidirectional buffer, and exchanging data between I/C ports.

[Effect]

When checking the interface IC, the signal to the external device is held by the latch and will not be lost.
This avoids a situation where the external device malfunctions due to signal loss during check.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

The figure shows an interface circuit according to an embodiment of the present invention. In the figure, 1 is a CPU, 2 is an interface ICl3 is an address decoding circuit, 4 is a bidirectional 3-state buffer, 5 is an output latch, 6 is an input buffer (3-state buffer), and 7 to 9 are NOT elements. , 10-13 are AN
D element, 14 is OR element, 15 is IC for binder face
2 control register, 16.17 is the interface IC20 input/output (I/O) port, and the CPU
1 and the interface IC 2 are the data bus 18, the 2° bit address line 24, the 2' bit address line 25, the information read signal line 26 of the CPU 1, and the C
The CPU 1 and address decode circuit 3 are connected by an address bus 19, the interface IC 2 and latches 5 and 6 are connected by data lines 20 and 21, and each latch 5
．． 6 and external devices not shown are data lines 22 and 25.
A buffer 4 is provided between the data lines 20 and 21, and the data lines 20 and 21 are connected to the buffer 4. The signal line 24 is connected to the input of the three-power AND element 10 via the NOT element 7.8.
．． 25 and the signal line 27 are connected, and the signal line 24 and 26 are connected to the input of the three-man power AND element 11, and the signal line 25 is connected via the NOT element 9.

The output signal lines 52 and 53 of the address decoding circuit 3 are connected to the input of the two-way OR element 140, and the output of the OR element 14 is input to the chip select terminal CS of the interface IC 2. The signal line 32 is further connected to the chip select terminal C5 of the buffer 4, and the signal line 33 is connected to one input terminal of each of the two-manual AND elements 12 and 13. A
The output signal lines 28 and 29 of the AND elements 10 and 11 are connected to other input terminals of the ND elements 12 and 15, respectively.
Output signal lines 50.31 of D elements 12.13 are connected to chip select terminals CS of husband latches 5 and 6. Signal lines 28,29 are also connected to buffer 4.

Next, the operation of the above-mentioned interface circuit will be explained.

The address decode circuit 3 decodes the address issued by the CPU 1, and outputs an 11" level signal to the signal line 32 if it is for checking the interface IC 2, and outputs an 11" level signal to the signal line 33 if it is for normal input/output. "Outputs H° level signal.

In the case of normal input/output, the °H° level signal of the signal line 33 is input to the interface IC 2 through the OR element 14, and the IC 2 is put into the operating state, and furthermore, the AND elements 12 and 13 are put into the through state. The signals on the signal lines 28 and 29 are input to the chip select terminal C5 of the latch 5.6. Editing input/output port 16 according to instructions from CPU 1
When selected, the output of the AND element 10 becomes "H" level, which is transmitted to the terminal CS of the latch 5, and the latch 5 becomes operable. Furthermore, when the input/output boat 17 is selected by the instruction from the CPU 1, the AND element 1
The output of 1 becomes the "H" level, which is transmitted to the latch 6, and the latch 6 becomes operational. This allows the CPU
1 and external devices can transfer data via data lines 22, 25, latches 5.6, data lines 20.21, IC2, and data bus 18.

When the address issued by the CPU 1 is for checking the IC 2, the signal level of the signal line 33 becomes @L" level, and the signal level of the signal line 32 becomes "Ho".

When the signal level of the signal line 33 reaches °L° level, AN
The output of the D element 12.15 becomes L" level, and therefore the latch 5.6 stops operating and holds data. Furthermore, even if the signal level of the signal line 33 becomes 1L" level, Since the signal level of the signal line 52 becomes 'H' and becomes a PEL, a signal is applied to the terminal CS of the IC2 through the OR element 14.
The H° level signal is input, and IC2 continues to operate. Then, the “H” level signal on the signal line 32 is transmitted to the buffer 4.
F) AND element 1 is input to the CS terminal of F), and the buffer 4 becomes operational.
When the output of 0 or 11 becomes °H'', the buffer 4 receives the ``H'' signal and the output direction of the buffer 4 is determined. Output port 16 → data line 20 → buffer 4 → data line 21 → input/output port 17 → data bus 18, or data bus 18 → input/output port 17 → data line 21 → buffer 4 → data line 2
0→I/O port 16→Data bus 1B route,
Return to CPU1. The CPU 1 compares the sent data with the returned data and checks the IC2.

As explained above, since the latch 5 holds the data signal sent to the external device when checking the interface IC 2, malfunction of the external device can be prevented.

〔Effect of the invention〕

According to the present invention, since the interface IC is checked while the signal to the external device is held, the check can be performed even while the external device is operating, which is effective in improving the reliability of the input/output interface. .

[Brief explanation of the drawing]

The figure is a configuration diagram of an interface circuit according to an embodiment of the present invention. 1 ・・・・・・・・・・・・・・・・・・CPU2・
・・・・・・・・・－・・・・・・・・・・Interface IC
3・・・・・・・・・・・・・・・・・・Address decoding circuit 4・・・・・・・・・・・・・・・Buffer 5.6・・・・・・...Latch 7-9...NOT elements 10-13...AND element 14...OR element agent
Patent Attorney Katsuo Ogawa

Claims (1)

[Claims] 1. Bidirectionality that interconnects an interface IC, a decoding circuit that can assign multiple addresses to the interface IC's control registers and I/O ports, and I/O ports in interfaces for microcomputers, etc. A failure diagnosis circuit for an interface IC, characterized by providing a bus driver and a buffer that separates an external device from the interface IC.