JPH01231132A - Dual processor - Google Patents

Abstract

PURPOSE:To execute a slow synchronizing control by providing a cache memory on a processor of an active system and a processor of a stand-by system, respectively and taking a synchronization of the processors of both the systems by a memory block replacing operation, when a mishit of the cache memories of both the systems has been generated. CONSTITUTION:It is assumed that a processor P0 of an active system is executing a processing by using a cache memory C0 of an active system, and a processor P1 of a stand-by system is executing a processing by using a cache memory C1 of the stand-by system. Write data which is generated in the processor P0 is written in a main storage M1, as well of the stand-by system by a duplex intersecting part X1 through a duplex intersecting part X0 and a duplex intersecting bus XB from a processor bus B0. In such a way, the identity of the contents of the main storage M0 of the active system and the main storage M1 of the stand-by system is held.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a duplex processing apparatus, and more particularly to a duplex processing apparatus in which two processing apparatuses are operated in a duplex synchronous manner.

[Conventional technology]

Conventionally, in this type of duplex processing device, the duplexed Koki t! By making the contents the same, it is possible to shorten the time required to change the system configuration and restart processing when an abnormality is detected in the information processing unit, input/output device, etc. As a method of making the contents of the duplicated main memories the same, there is a method of synchronizing the duplicated processors at the clock level to execute the same processing.

However, as processors become faster in recent years, it has become technically difficult to synchronize processing in active processors and standby processors at the clock level.

Therefore, a method has been adopted in which only the active system processor performs processing, and the contents of the active system's main memory that change during processing are also written to the standby system's main memory, making the contents of the main memory of both systems the same. This is becoming more and more common. In this method, the standby processor and its associated peripheral circuits are stopped and controlled not to access the standby main memory.

[Problem to be solved by the invention]

In the conventional redundant processing device described above, the standby processor starts operating as the new active processor only when a failure occurs in the active processor and the system configuration is changed. If there is a latent defect in the standby processor, both the active and standby processors may become abnormal when the system configuration is changed, and in the worst case, the system may go down. It has the disadvantage of being sexual.

On the other hand, in recent years, processors have become faster, but with single-level large-capacity main memory, the slow access speed of the memory system has made it impossible to bring out the inherent high speed of the processor, and high reliability is required. There is an increasing need to introduce cache storage in duplex processing devices.

In view of the above-mentioned points, an object of the present invention is to introduce cache memory also in a redundant processing device to bring out the high speed of the processor, and to utilize a mishit detection signal in the cache memory to detect errors in active processing devices and To provide a redundant processing device in which standby processing devices are operated synchronously at a gentler level than the clock level.

[Means to solve the problem]

A duplex processing device of the present invention includes active and standby main memories, active and standby processors, and active and standby processor buses. A redundant crossing means connects the active system processor to the main memory of the active system and writes data written to the main memory of the active system to the main memory of the standby system, and a cache of the other system that detects a miss caused by an access from the processor of the own system. A connection between active and standby cache memory that starts memory block replacement from its own main memory when a mishit detection signal from memory is detected, and these active and standby cache memories. and a control line for transmitting the mishit detection signal.

[Effect]

In the duplex processing device of the present invention, the duplex crossing means connects the processor buses and writes data written by the active processor to the active main memory also to the standby main memory. When the cache memory detects a miss due to an access from the processor of the own system and a miss-hit detection signal from the cache memory of another system is detected, the memory block replacement operation from the main memory of the own system is started and controlled. Eight lines connect active and standby cache memories and transmit mishit detection signals.

【Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the duplex processing device of the present invention.
A processor PO1, a processing device including a main memory MO, a cache memory CO, and a processor bus BO (hereinafter, this processing device is referred to as an O-system processing device), a processor PI,
Main memory Ml.

A processing device including a cache memory C1 and a processor bus B1 (hereinafter, this processing device will be referred to as a 1-system processing device), and a duplex intersection x connected to the processor bus BO.
O and a redundant intersection X connected to the processor bus B1
1, a duplex crossover bus XB that connects the duplex intersection XO and the duplex intersection X1, and control lines MHO and MH that connect the cache memory CO and the cache memory C1.
The main part is composed of I.

A redundant processing device consists of an active processing device and a standby processing device. Normally, the active processing device executes online processing, and the standby processing device is positioned as a standby system. Hereinafter, for the sake of explanation, the 0-system processing device is assumed to be an active-system processing device, and the ①-system processing device is assumed to be a standby-system processing device.

Next, the operation of the duplex processing apparatus of this embodiment configured as described above will be explained with reference to the timing charts shown in FIG. 2 (al to el).

Currently, the active processor processor PO is executing processing using the active cache storage CO, and the standby processor P1 is executing processing using the standby cache storage C1.

Here, when write data is generated in the active processor PO, the write data is written from the processor PO to the cache memory 1ICo, and at the same time, the write data is written to the main memory MO via the processor bus BO as a write-through operation. Data is written (second
(see figure fat). In addition, write data generated in processor PO is transferred from processor bus BO to duplex intersection XO.
and via the redundant crossover bus XB (see Figure 2 (bl)), the main memory M of the standby system is
1 (see FIG. 2 (C1)), thereby maintaining the identity of the contents of the active main memory tQMo and the standby main memory M1.

On the other hand, corresponding write data is also generated in the standby processor P1 that executes the same process as the active processor PO, but the standby cache memory CI performs a write-through operation for the standby processor tαM1. Therefore, the write data processing in the standby cache memory tICI is executed faster than the write data processing in the active cache memory CO, and the standby The system cache memory CI returns a response faster than the active system cache memory (Bo).

Therefore, between one miss hit and the next miss hit, 1
Except for the rare case where there is no write and only read, the processing of the standby processor PI precedes the processing of the active processor PO. In addition, even in the rare case that no writes occur between one mishit and only one read, the standby processor P1's processing and It can be considered that the processing is performed at the same time as the processing by the active processor PO.

If a miss occurs in the cache memory C1 due to an access from the processor P1 while the process of the standby processor PI is being executed before or simultaneously with the process of the active processor PO, the cache memory C1 Kara system? A mishit detection signal is issued to 11fiMH1 (see tel in FIG. 2).

On the other hand, delayed or simultaneously, a miss occurs in the cache memory CO due to an access from the processor PO, and a miss detection signal is issued from the cache memory CO to the control line MHO (see id+ in FIG. 2).

Active cache storage CO and standby cache storage CI are connected to control lines MHO and MHI.
After the miss detection signals of both become active, the data transfer for the memory block replacement operation is started simultaneously between the main memory MO and the cache memory (QCO) and between the main memory M1 and the cache memory C1 (Figure 2+al and (See C1), in other words, when the mishit detection signals of the control lines MHO and MHI both become active, the active processor PO and the standby processor P1
synchronization of operations is achieved.

By the way, as mentioned above, since the active processor PO is processing earlier than or at the same time as the standby processor Pl, even when a mishit occurs, it is necessary to synchronize with the standby processor Pl. There is no waiting time, processing can be performed at the same speed as during asynchronous operation, and the original business such as online processing is not affected.

〔Effect of the invention〕

As explained above, the present invention provides cache storage in each of the active processing device and the standby processing device, and when a cache storage mishit occurs in both systems, the processors in both systems are synchronized by the memory block M recall operation. By making the process *'R
This has the effect of making it possible to realize duplex synchronous operation using more gradual synchronous control instead of clock level synchronous control.

In addition, the standby processor can perform the same processing as the active processor without reducing the processing speed of the active processor, and when changing the system configuration, the standby processor's potential Since there is no possibility that a system failure will occur due to a defect, the reliability of the duplex processing device can be significantly improved compared to the conventional operation in which a standby processor is stopped.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the duplexing processing device of the present invention, and FIGS. 2(a-1) to (e) are timing charts showing the operation of the duplexing processing device of the present embodiment. In the figure, PO, Pl... Processor, MO, M!... Main memory, CO, CI... Cache memory, BO, Bl... Processor bus, XO, XI... Duplex intersection, XB... ...duplex crossover bus, MHO, MHI/control lines.

Claims (1)

[Scope of Claims] In a duplex processing device including active and standby main memories, active and standby processors, and active and standby processor buses, the processor buses are connected. There is also a redundant intersection means for writing data written by an active processor to the active main memory into the standby main memory, and a redundant crossing means that detects a miss caused by an access from the own processor and writes data from the cache memory of the other system. The active system and standby system cache memory that starts memory block replacement operation from the own system's main memory when a mishit detection signal is detected, and these active system and standby system cache memories are connected. A duplex processing device comprising: a control line for transmitting the mishit detection signal.