JPS5932807B2 - Clock switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has dual computers and the above two
In an information processing system configured so that multiple computers commonly use one clock source, when the current clock source turns off, another clock source is immediately used. .

As a conventional information processing system having dual computers that operate on the same clock source, for example, the one shown in FIG. 1 is known.

In FIG. 1, 1a and 1b are computers, 2a and 2b are main memories, 3a and 3b are refresh circuits, 4a and 4b are 0R circuits, 5a and 5b are AND circuits with negative gates, and 6a
, 6b is an AND circuit, 7a and 7b are clock sources, 8a,
Reference numeral 8b indicates a clock off detection circuit, and reference numeral 9 indicates a clock management circuit. The main memories 2a and 2b require refreshing like dynamic C memories. The clock off detector 8a has, for example, an integrator therein, and outputs a logic "0" if the clock source 7a is off for a predetermined period of time. Clock off detector 8b operates in a similar manner. The clock management circuit 9 has, for example, an internal flip-flop for clock switching.
It has a flop (not shown), and if it is in the set state, it outputs "0" to the signal line La and "l" to the signal line Lb.
This outputs the following. In the reset state, the states of the signal lines La and Lb are reversed. Further, the clock management circuit has an internal clock source (not shown), and this clock source is slower than the clock sources 7a and 7b. The computers 1a and 1b use the same clock source and process work in synchronization with each other.

It is now assumed that the clock source 7a is being used. At this time, the signal line La is at "0" and the signal line Lb is at "1". Since the signal line La is [0], the AND circuit 5a is opened and the clock from the clock source 7a is connected to the AN
The signal is supplied to each part of the computer 1a through the D circuit 5a and the 0R circuit 4a. This clock is a refresh circuit 3a.
Also supplied. The refresh circuit 3a counts this clock and refreshes the main memory 2a at predetermined intervals. As for the computer 16, since the signal line Lb is "1", the AND circuit 6b is opened, and the clock from the clock source 7a is passed through the AND circuit and the 0R circuit 4b to the computer 1.
It is supplied to each part of b. This clock is also supplied to the refresh circuit 3b, which counts this clock and refreshes the main memory 2b at predetermined intervals. Assume that the current clock source 7a is turned off due to a failure or other cause.

The clock off detection circuit 8a detects that the clock is turned off and outputs a clock off detection signal of "O". This clock off detection signal is sent to the clock management circuit 9. When the clock management circuit 9 receives the clock off detection signal, it switches the internal flip-flop to set "l" to the signal line La and to the signal line Lb. Outputs "O". As a result, the clock source used is switched from the clock source 7a to the clock source 7b, and the computers 1a and 1b are clocked from the clock source 7b.
It operates on the clock source from a. However, as mentioned above, because the clock-off detector 8a has an integrator inside it and the clock management circuit 9 operates with a low-speed clock, the clock 7a may turn off. It takes a considerable amount of time until the clock management circuit 9 sends a clock switching command to the signal lines La and Lb.

Since the clock does not arrive, the counter that measures time stops, and as a result, the refresh signal to the main memories 1a and 1b is not output even after a predetermined period of time has elapsed and is interrupted, causing the storage contents of the main memories 2a and 2b to be destroyed. may be done.
The present invention aims to eliminate the above-mentioned drawbacks, and provides for an information processing system having multiplexed computers and configured such that the two computers use a common clock source. The purpose is to immediately use another clock source when the current clock is turned off.

Therefore, the clock switching method of the present invention includes an A-system computer, a B-system computer, and a clock management circuit, and the A-system computer includes a memory that requires refreshing, a clock source, A clock off detection circuit detects whether or not the clock source is turned off; and a clock off detection circuit detects whether or not the clock source is turned off; The B-system computer has a clock switching gate that supplies each part of the system computer, and the B-system computer has a memory that requires refreshing, a clock source, and a clock off detection circuit that detects whether or not the clock source is turned off. and a clock switching gate that supplies either the clock output from the clock source of the A-system computer or the clock source output from the B-system computer to each part of the B-system computer, The circuit is
One clock switching gate is supplied with a clock selection signal of a predetermined value indicating that the clock from its own clock source should be used, and the other clock switching gate is supplied with a clock from the other system's clock source. In addition to supplying a clock selection signal with another predetermined value to instruct that the clock should be used, the clock source status signal output from the clock off detection circuit of system A and the output of the clock off detection circuit of system B is supplied. If one of the clock source status signals indicates that the clock is off, the clock switching gate of the system corresponding to the clock source status signal is set to another predetermined value. It is configured to supply a clock selection signal and also supply a clock selection signal of a predetermined value to the clock switching gate of the other system, and each of the clock switching gate of system A and the clock switching gate of system B is connected to the clock switching gate of the other system. A clock from a clock source of another system, a clock from a clock source of another system, a clock from the own system's clock source.
The clock source state signal from the off detection circuit, the clock source state signal from another system's clock off detection circuit, and the clock selection signal from the clock management circuit are input,
If the clock source status signals of both systems do not indicate clock off, the clock from the clock source of the system specified by the clock selection signal is output, and either one of the clock source status signals indicates clock off. In the case shown, the circuit is characterized in that it is configured to output a clock from a clock source of a system corresponding to another clock source status signal, regardless of the clock selection signal. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the present invention, in which 11a and 11b are computers,
12a, 12b are main memories, 13a, 13b are refresh circuits, 14a, 14b are 0R circuits, 15a, 15b
16a, 16b are AND circuits, 17a, 17b are clock sources, 18a, 18b are clock off detection circuits, 19 is a clock management circuit, 20
a, 20b, 21a, 21b are NAND circuits, 22a,
22b, 23a, and 23b each indicate a signal line. The main memories 12a and 12b require refreshing, such as dynamic 1C memories. Refresh circuits 13a and 13b operate in the same way as refresh circuits 3a and 3b in FIG. 1. clock
The off detection circuits 18a and 18b operate in the same way as the clock off detection circuits 8a and 8b shown in FIG.
It performs the same operation as . Now clock source 17
Assume that both a and 17b are in the on state.

Both clock off detection circuits 18a and 18b output "1". Assuming that the signal line 22a is [0],
The output of the NAND circuit 21a is "1", the NAND circuit 20
The output of a is "0", and the clock from the clock source 17a is supplied to the refresh circuit 13a of the computer 11a and others through the AND circuit 15a and the 0R circuit 14a. The refresh circuit 13a counts the clocks,
The main memory 12a is refreshed at predetermined intervals. When the signal line 22a is [0], the signal line 22b is "1", so the output of the NAND circuit 21b is "01", and the output of the NAND circuit 20b is [1], and the AND circuit 16b is opened.

Therefore, the clock from clock source 17a is AND
The signal is supplied to the refresh circuit of the computer 14b and others through the circuit 16b and the 0R circuit 14b. When the current tally clock source 17a is turned off, the clock off detection circuit 18a outputs "0".

Therefore, the NAND circuit 20a outputs "1" regardless of the signal on the signal line 22a. And clock source 17
The clock from b is connected to the AND circuit 16a and the 0R circuit 14.
The signal is supplied to the refresh circuit 13a of the computer 11a and others through the line a. At this time, clock off detection circuit 1
The tarlock off detection signal from 8a is also sent to clock management circuit 19. Upon receiving this clock off detection signal, the tally management circuit 19 switches the internal flip
Switch the flop (not shown) and set "1" to the signal line 22a.
and outputs "0" to the signal line 22b. NAND circuit 2
1b outputs "1" since the signal line 23a is "0".

Since the clock source 17b is in the on state, the clock off detection circuit 18b outputs "1". For this reason,
The NAND circuit 20b outputs "0", and the AND circuit 15
Open b. The clock from clock source 17b is AND
computer 11b through circuit 15b and clock source 14b.
It is supplied to the refresh circuit 13b and others. Even if the failure of the clock source 17a is repaired and the clock source 17a is turned on, the clock management circuit 19 will not operate the signal line 22.
Since "1" is output to signal line a and "O" is output to signal line 22b, the clock is not switched.

As is clear from the above description, according to the present invention, in an information processing system that has two duplex computers and commonly uses one clock source, when the current clock source is turned off, the other clock source is immediately turned off. Since the clock source is configured to use the same clock source, it is possible to prevent failures due to interruption of the clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional duplex information processing system, and FIG. 2 is a block diagram of one embodiment of the present invention. 11a, 11b... Calculator, 12a, 12b.
．． ,...main memory, 13a, 13b...refresh circuit, 14a, 14b...0R circuit,
15a, 15b...AND circuit with negative gate,
16a, 16b...AND circuit, 17a, 17
b...Clock source, 18a, 18b...
・Clock off detection circuit, 19...Clock management circuit, 20a, 20b, 21a, 21b...
・NAND circuit, 22a, 22b, 23a, 23b...
····Signal line.

Claims (1)

[Claims] 1 Equipped with an A-system computer, a B-system computer, and a clock management circuit, the A-system computer has a memory that requires refreshing, a clock source, and a system that detects whether or not the clock source is turned off. A clock off detection circuit for detecting a clock off, and a clock switching gate that supplies either the clock output from the clock source of the A-system computer or the clock output from the clock source of the B-system computer to each part of the A-system computer. The B-system computers have a memory that requires refreshing, a clock source, a clock off detection circuit that detects whether the clock source is turned off, and a clock source for the A-system computers. a clock switching gate that supplies either the output clock or the clock source output from the B-system computer to each part of the B-system computer; For the other clock switching gate, supply a clock selection signal with a predetermined value indicating that the clock from the clock source of the own system should be used, and for the other clock switching gate, the clock from the clock source of the other system should be used. supplying a clock selection signal with another predetermined value that instructs the above, and monitors the clock source state signal output from the A-system clock-off detection circuit and the clock source state signal output from the B-system clock-off detection circuit. However, if either one of the clock source status signals indicates clock off, the clock selection signal with another predetermined value is supplied to the clock switching gate of the system corresponding to the clock source status signal. It is configured to supply a clock selection signal of a predetermined value to the clock switching gate of the other system, and each of the clock switching gate of the A system and the clock switching gate of the B system receives the clock from the clock source of the own system, Inputs the clock from the other system's clock source, the clock source state signal from the own system's clock off detection circuit, the clock source state signal from the other system's clock off detection circuit, and the clock selection signal from the above clock management circuit. Then, the clock source status signals of both systems are both clock
If it does not indicate OFF, outputs the clock from the clock source of the system specified by the clock selection signal, and if either clock source status signal indicates clock OFF, it outputs the clock from the clock source specified by the clock selection signal. 1. A clock switching method characterized in that the clock switching method is configured to output a clock from a clock source of a system that corresponds to another clock source status signal.