JPH03144992A - Method and device for holding data of mass storage memory using nonvolatile memory - Google Patents

Abstract

PURPOSE:To make the device small and inexpensive on the whole by refreshing the nonvolatile memory with a signal for generating refresh timing (RT) from an RT signal generating circuit and an arbritrating circuit. CONSTITUTION:When a microprocessor 3 starts access, an address signal S2 is generated and inputted to a memory selection part 14 and an address switching circuit 20 and the selection part 14 outputs a memory select signal S3 to the arbitrating circuit 15 when the signal corresponds to an address indicating the nonvolatile memory 12. The circuit 15 arbitrates an RT signal S1 outputted by a frequency divider 13 and the signal S3 from the selection part 14 and outputs the signal S3 to a delay element 16 and a switching part 19, which outputs the signal S3 to the memory 12 as a column address strobe signal. The element 16 inputs the signal S4 generated by delaying the signal S3 to an address switch 20 to perform switching from a column address to a row address and outputs it to the memory 12. A delay element 17 delays the signal S4 to input its to the memory 12 as a row address strobe signal, thereby refreshing the memory 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides system setting parameters in a processor application device, data outputted from the device to the outside, etc., when the main power of the device is turned off. hold even after being
Concerning data retention methods and devices for devices that reuse this retained data when the main power of the device is turned on again,
In particular, the present invention relates to a data retention method and apparatus for a large-capacity memory using volatile memory.

[Prior art]

Conventionally, data retention in a microprocessor application device has been realized by a configuration as shown in FIG. The microprocessor 3 is supplied with power from the main power supply 6 and is powered by the oscillator 1.
At this timing, data in the nonvolatile memory 5 is referenced and updated through the control of the microprocessor peripheral section 2 and the memory control section 4.

In FIG. 4, when the voltage of the main power supply 6 drops to a level that makes the operation of the microprocessor 3 unstable, the memory control unit 4
switches the power supply to the nonvolatile memory 5 from the main power supply 6 to the backup power supply 7, and at the same time prohibits the microprocessor 3 from referencing and updating the nonvolatile memory 5,
The data stored in the non-volatile memory 5 was held.

FIG. 5 is a block diagram showing a detailed configuration of the memory control section 4 in FIG. 4. As shown in FIG.

As shown in FIG. 5, the memory control unit 4 constantly monitors the output of the main power supply 6 and the memory select unit 8 that outputs selection information to the nonvolatile memory 5 based on the address information from the microprocessor 3. When the voltage drops below a certain level,
A power supply control unit 10 switches the power supply to the nonvolatile memory 5 from the main power supply 6 to a backup power supply 7, and a signal from the power supply control unit 10 allows the microprocessor 3 to refer to the nonvolatile memory 5, permit or prohibit updating. The memory input/output control unit 19 is roughly divided into three components.

[Problem to be solved by the invention]

In the conventional example described above, the inside of the memory control unit 4 does not have a complicated structure, but as the amount of data to be held increases, a large amount of relatively expensive non-volatile memory 5 is required. In order to implement this non-volatile memory, a large space is required, resulting in a large and expensive device.

[Means to solve the problem]

In order to solve the above-mentioned problems, the method of the present invention has the following advantages: As shown in FIGS. The refresh signal Ss =
The generated refresh signals s, ,
By inputting Ss into the volatile memory 12, the volatile memory 12 is automatically refreshed, and the oscillator 1' and the first . Second and third delay elements and switching section 19
．． By backing up the volatile memory 12, the refresh timing generation circuit 13, and the arbitration circuit 15 from the backup power supply 7, the contents of the volatile memory 12 are retained regardless of the state of the main power supply 6.

In order to solve the same problem, the device of the present invention includes a circuit 13 that generates a refresh timing signal S1 during a refresh cycle of a volatile memory 12 that requires a refresh operation to retain memory, as shown in the first and second figures. Refresh timing signal S.

and a circuit 15 that outputs a signal S3 that arbitrates accesses from the processor 3 and creates a refresh timing during a refresh cycle, and a volatile memory 12 that receives a refresh timing signal 53 output from this arbitration circuit 15.
a refresh signal Ss for refreshing, a refresh signal generating means 21 for outputting Ss, and an oscillator 1'
, and the first. Second. Third delay element and switching section 19. Volatile memory 12. IJ fresh timing generation circuit 1
3 and a backup power supply 7 for backing up the arbitration circuit 15.

[For production]

The signal 53 that generates the refresh timing output from the refresh timing signal generation circuit 13 during the refresh cycle and the access from the processor 3 are connected to the arbitration circuit 1.
5, the signal S3 that creates the refresh timing to be output is sent to the refresh signal generating means 21.
The refresh signal Ss inputted to and outputted from this
, S8, the volatile memory 12 is refreshed and data is retained.

〔Example〕

The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an overview of the structure of an embodiment of the method and apparatus of the present invention, and FIG. 2 is a block diagram showing the structure in detail.

First, the configuration of this embodiment will be explained.

Data retention in this embodiment is as follows. This is realized by a configuration as shown in the second diagram.

The microprocessor 3 uses the timing of the oscillator 1 to
Controls the microprocessor peripheral section 2. References and updates to the volatile memory 12 from the microprocessor 3 are performed through the memory control B11.

A frequency divider 13 generates a refresh timing signal 53 by dividing the output of the oscillator I until the period at which the volatile memory 12 needs to be refreshed, and a frequency divider 14 generates an address signal S2 generated in the processor 3 at the start of access. a memory select unit that outputs a memory select signal S3 when the input address signal S2 is a signal pointing to the volatile memory 12;
15 inputs the refresh timing signal Sl and the memory select signal S3, arbitrates between them, and outputs the memory select signal S3 when only the memory select signal 53 is input; 9 outputs the switching signal S8 when the refresh timing signal 53 is input. , and a refresh cycle signal S7 indicating to the microprocessor 3 that a refresh cycle is in progress.
This is an arbitration circuit that outputs

19 outputs the memory select signal 53 as a column address strobe signal to the volatile memory 12 as it is when the switching signal 53 is not input from the arbitration circuit 15, and outputs the memory select signal 53 as a column address strobe signal to the volatile memory 12 as it is, and when the switching signal S0 is input, it outputs the memory select signal 53 as a column address strobe signal to the volatile memory 12. Element 18
A switching unit 16 outputs the output signal S6 as a column address strobe signal, and 16 is a memory select signal output from the arbitration circuit 15 or a signal 5 that creates a refresh timing.
17 is a second delay element that delays the signal S4 output from the first delay element 16 for a certain period of time and outputs it to the volatile memory 12 as a row address strobe signal 53, 18 is a third delay element that delays the output signal 53 of the second delay element 17 by a certain period of time and outputs the delayed signal to the switching section 19.

20 is an address switch which inputs the output signal S4 of the first delay element 16 and the address signal S2 and outputs the output signal 53 as an address switching signal to the volatile memory U12 of the address signal 53.

7 is a backup power source for backing up the volatile memory 129, frequency divider 13 and arbitration circuit 15, and 6 is a main power source.

The memory control unit 11 includes a frequency divider 13. Memory select section 14
, arbitration circuit 15. The refresh signal generation means 21 includes first to third delay elements 16 to 18, a switching section 19, and an address switch 20.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

First, the operation of the microprocessor 3 to access the volatile memory 12 will be described.

When microprocessor 3 starts accessing, address signal S2 is generated. This address signal S2 is input to the memory select section 14 and address switch 2 (12). The memory select section 14 outputs a memory select signal S3 to the arbitration circuit 15 when the input address signal 53l is an address pointing to the volatile memory 12. The arbitration circuit 15 arbitrates between the fresh timing signal S1 output from the frequency divider 13 and the memory select signal S3 output from the memory select B14, and outputs the memory select signal S.
In the case of only 3 inputs, the memory select signal S3 is output to the first delay element 16 and the switching section 19 as is. Switching signal S8. The output of the IJ fresh cycle signal 53 does not change. Since the switching unit 19 does not receive the switching signal S8, it directly outputs the memory select signal S3 to the volatile memory 12 as a column address strobe signal.

The first delay element 16 delays the memox 1/cut signal S3 for a certain period of time, and the second delay element 17 and the address switch 2 (
12). The address switch 20 switches the address signal S2 from a column address to a row address in response to the output signal 53 from the first delay element 16 and outputs it to the volatile memory U12. SI1 is the output signal of the address switch 20.

The second delay element 17 delays the output signal S4 of the first delay element 16 by a certain period of time and outputs it to the volatile memory 12 and the third delay element 18 as a row address strobe signal.

The third delay element 18 receives the output signal S of the second delay element 17.

is delayed for a certain period of time to generate a refresh signal S6, which is output to the switching section 19.

The reason why addresses are inputted in a time-division manner in this manner is that addresses are inputted in a time-division manner in order to reduce the external dimensions of the volatile memory 12.

Next, the operation of rewriting the contents of the volatile memory 12 will be described. Memory refresh uses the volatile memory 12, which is refreshed by swapping the timings of the column address signal and row address signal.
This is achieved by swapping the timings of the column address signal and row address signal.

The refresh timing signal S1 is generated by frequency dividing the output of the oscillator 1' by a frequency divider 13 to a period at which the volatile memory 12 needs to be refreshed.

Since this frequency-divided signal is not directly related to the operation of the MPU, the same oscillator 1' as the oscillator 1 may be used to reduce costs. The refresh timing signal Sl generated by the frequency divider 13 is input to the arbitration circuit 15. The arbitration circuit 15 receives this input and determines whether there is an access from the microprocessor 3 through the memory select section 14. When there is an access from the microprocessor 3, it waits until the access is finished, and if there is no access, it immediately outputs the switching signal 53 from the arbitration circuit 15 to the switching section 19, and also outputs a refresh cycle signal 53 indicating that the refresh cycle is in progress. is output to the microprocessor 3. At the same time, a signal 53 for creating refresh timing is output to the first delay element 16 and the switching section 19.

When the refresh cycle signal 53 from the arbitration circuit 15 is input, the microprocessor 3 performs a refresh operation.
To avoid memory access contention, memory access is performed using the refresh cycle signal S.

Don't do it until it runs out.

The first delay element 16 receives a signal S3 from the arbitration circuit 15 that creates a refresh timing, and receives the signal S3.

The address switch 20 switches the address input to the volatile memory 12 based on the output of the first delay element 16. (However, during refresh, the address that is input to the volatile memory 12 is output to the address switch 20 and the second delay element 17. address input will be ignored.

The second delay element 17 receives the output signal S4 of the first delay element 16, delays the signal 53 for a certain period of time, and outputs the delayed signal to the volatile memory 12 and the third delay element 18. volatile memory 1
2, the output signal Ss of the second delay element 17 is inputted as a row address strobe signal.

The third delay element 18 receives the output signal S5 of the second delay element 17.
is output to the switching section 19 after a certain period of delay. Switching section 19
Since the switching signal 53 is inputted from the arbitration circuit 15, the output signal S6 of the third delay element 18 is outputted to the volatile memory 12 as a column address strobe signal.

At this time, since the row address strobe signal 53 has already been input to the volatile memory 12, the volatile memory 12 enters the refresh mode as described above, and the memory 12
The data within is automatically refreshed.

〔Effect of the invention〕

As described above, according to the present invention, the refresh request from the circuit 13 that generates the refresh timing signal SI and the access from the processor 3 are arbitrated during the refresh cycle of the volatile memory 12 that requires a refresh operation for memory retention. The refresh signal s, , 53! By inputting the generated refresh signals Ss and Ss to the volatile memory 12, the volatile memory 12 is automatically refreshed, and the volatile memory 12. The refresh timing generation circuit 13 and the arbitration circuit 15 are powered by a backup power supply 7.
This data retention method and device is characterized by retaining the contents of the volatile memory 12 regardless of the state of the main power supply 6 by backing up the contents of the volatile memory 12. By replacing this with a small-sized volatile memory 12 and configuring a circuit for refreshing this volatile memory 12, the entire device that requires data retention in a large-capacity memory can be made smaller and cheaper.

[Brief explanation of drawings] 1st ri! J is a block diagram showing an overview of the configuration of one embodiment of the method and apparatus of the present invention, FIG. 2 is a block diagram showing the configuration in detail, and FIG. 3 is a timing chart for explaining the operation of this embodiment. , FIG. 4 is a block diagram showing an overview of an example of a conventional method and apparatus, and FIG. 5 is a block diagram showing its configuration in detail. 3... (micro) processor, 6...
・Main power supply, 7... Backup power supply, 12...
... Volatile memory, 13 ... Refresh timing signal generation circuit (frequency divider), 14 ...
Memory selection section, 15... Arbitration circuit, 16.
...First delay element, 17... Second delay element, 18... Third delay element, 19...
Switcher, 21... Refresh signal generating means,
Sl...Refresh timing signal, S2'...
...Address signal, Ss...Memory select signal, signal for creating refresh timing 9 column address strobe signal, 53...First delay element 16
output signal, S5... Refresh signal (second
Output signal of delay element 17 (2-row address strobe signal)
, Sl...Refresh signal (third delay element 18
output signal 9 column address strobe signal), S7...
...Refresh cycle signal, Sa...Switching signal. Paper 1 Hakusan 9 A

Claims (3)

[Claims] (1) Arbitrates between the refresh request from the circuit (13) that generates the refresh timing signal S_1 during the refresh cycle of the volatile memory (12) that requires a refresh operation for memory retention, and the access from the processor (3) The circuit (15) automatically generates refresh signals S_5, S_6, and the generated refresh signals S_5, S_6 are input to the volatile memory (12) to automatically refresh the volatile memory (12). together with an oscillator (1'), first, second, and third delay elements, a switching section (19), and a volatile memory (12).
), the refresh timing generation circuit (13) and the arbitration circuit (15) are backed up by the backup power supply (7), so that the contents of the volatile memory (12) can be retained regardless of the state of the main power supply (6). A data retention method in large-capacity memory using volatile memory. (2) a circuit (13) that generates a refresh timing signal S_1 during a refresh cycle of a volatile memory (12) that requires a refresh operation to retain memory;
This refresh timing signal S_1 and the processor (
A circuit (15) that outputs a signal S_3 that arbitrates access from the volatile memory (3) and creates a refresh timing during a refresh cycle, and a refresh timing signal S_1 output from this arbitration circuit (15) is input to the volatile memory (15).
12) refresh signal S_5 for refreshing;
A refresh signal generating means (21) that outputs S_6, an oscillator (1'), a volatile memory (12) of the first, second and third delay elements and a switching section (19), and a refresh timing generation circuit. A large-capacity memory data holding device using a volatile memory consisting of a backup power source (7) that backs up a road exit and an arbitration circuit (15). (3) a circuit (13) that generates a refresh timing signal S_1 during a refresh cycle of the volatile memory (12) that requires a refresh operation to retain memory;
When the address signal S_2 of the processor (3) generated at the start of access is input and the address signal S_2 is a signal pointing to the volatile memory (12), a memory select signal S_3 is generated.
A memory select section (14) that outputs a
When the refresh timing signal S_1 is input, the memory select signal S_3 is outputted, and when the refresh timing signal S_1 is inputted, the signal S_3 that creates the refresh timing and the switching signal S_8 are outputted, and the refresh cycle signal S_7 indicating that the refresh cycle is in progress is sent to the processor (3). An arbitration circuit (15) outputs a switching signal S_ from this arbitration circuit (15) to
8 is not input, the memory select signal S_3 is output as a column address strobe signal to the volatile memory (12), and when the switching signal S_8 is input, it is output as the output signal of the third delay signal (18) described later. a switching unit (19) that outputs S_6 as a column address strobe signal;
A first delay element (16) that delays the memory select signal output from the arbitration circuit (15) or the signal S_3 that creates the refresh timing by a certain period of time and outputs the signal S_4 output from the first delay element (16) for a certain period of time. A second delay element (17) outputs the delayed row address strobe signal S_5 to the volatile memory (12), and outputs the output signal S_5 of the second delay element (17) to the switching unit (19) after delaying it by a certain period of time. a third delay element (18),
An oscillator (1'), first, second, and third delay elements and switching units (19), a volatile memory (12), a refresh timing signal generation circuit (13), and an arbitration circuit (15).
) A large-capacity memory data retention device using a volatile memory consisting of a backup power source (7) for backing up the power source (7).