JP2664258B2 - Method and apparatus for holding data in large-capacity memory using volatile memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a processor applied device in which a main power supply of a device disconnects a system setting parameter in the device and data output from the device to the outside. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for retaining data after the data has been stored and reusing the retained data when the main power of the apparatus is turned on again, and in particular, a method for retaining data in a large-capacity memory using a volatile meter. And an apparatus.

[Conventional technology]

Conventionally, data retention of microprocessor application equipment
This is realized by the configuration as shown in FIG. The microprocessor 3 is supplied with power from the main power supply 6, controls the microprocessor peripheral unit 2, and refers to and updates data in the nonvolatile memory 5 through the control of the microprocessor peripheral unit 2 and the memory control unit 4 at the timing of the oscillator 1. .

In FIG. 4, when the voltage of the main power supply 6 decreases to a level at which the operation of the microprocessor 3 becomes unstable, the memory control unit 4 switches the power supply to the nonvolatile memory 5 from the main power supply 6 to the backup power supply 7, At the same time, the reference and update of the nonvolatile memory 5 from the microprocessor 3 are prohibited, and the data stored in the nonvolatile memory 5 is held.

FIG. 5 is a block diagram showing the configuration when the configuration of the memory control unit 4 is shown in detail in FIG.

As shown in FIG. 5, a memory control unit 4 outputs a select information to a nonvolatile memory 5 based on address information from the microprocessor 3 and a main power supply 6.
And a power supply control unit 10 for switching the power supply to the nonvolatile memory 5 from the main power supply 6 to the backup power supply 7 when the voltage drops below a certain voltage. It is roughly divided into three components of a memory input / output control unit 9 for referring to the non-volatile memory 5 from the processor 3 and permitting / prohibiting updating.

[Problems to be solved by the invention]

In the conventional example as described above, the inside of the memory control unit 4 does not have a complicated structure. However, when the amount of data to be stored increases, a relatively expensive nonvolatile memory 5 needs to be increased. There is a problem that a large space is required to mount the nonvolatile memory, and the device becomes large and expensive.

[Means for solving the problem]

In order to solve the above-mentioned problem, the method of the present invention, as shown in FIGS. 1 and 2, uses a reference timing signal from the oscillator 1 'when a refresh operation of the volatile memory 12 requiring a refresh operation for storing data is enabled. and refresh enable signals S ₁ to output from this is input to the refresh timing signal generation circuit 13 that arbitrates the memory select signal Sse outputs than this by entering the starting time of access address signal S from the processor 3 to the memory select part 14 The refresh timing signal S ₃ arbitrated by the circuit 15 and output from the circuit 15 when the refresh enable signal S ₁ or the memory select signal Sse is input is delayed by the refresh signal generation means 21 using a delay element, and the refresh signal S ₅ , taken out S _6, the refresh timing signal S ₃ is output at the arbitration circuit 15 And switching the output at a refresh signal S ₆ the switching unit 19 obtained from the refresh signal generating means 21, a refresh signal S ₅ obtained from the refresh signal S ₁₀ and the refresh signal generating means 21 obtained from this switching section in the volatile memory 12 By inputting, the volatile memory 12 is automatically refreshed,
The volatile memory 12, the refresh timing generation circuit 13, and the arbitration circuit 15 are backed up by the backup power supply 7, so that the contents of the volatile memory 12 are retained regardless of the state of the main power supply 6.

In order to solve the same problem, the device of the present invention, as shown in FIGS. 1 and 2, shows the oscillator 1 ′ when the volatile memory 12 which requires a refresh operation for storing data is refresh-enabled.
A circuit 13 for generating a refresh enable signals S ₁ to input timing signal as a reference from the memory to output from this by entering the address signal S from the refresh enable signals S ₁ and the processor 3 to the memory select part 14 arbitrates the select signal Sse, a circuit 15 for outputting a refresh timing signal S ₃ and the switching signal S ₈ used during refresh enable inputs a refresh timing signal S ₃ is output at the arbitration circuit 15 a volatile memory
Refresh signal generating means 21 using delay elements for outputting refresh signals S ₅ and S ₆ for performing a refresh of 12
When a refresh timing signal S ₃ is output at the arbitration circuit 15, a switching unit 19 for outputting switching the refresh signal S ₆ obtained from the refresh signal generating means 21, the volatile memory 12, the refresh timing generating circuit 13 and the arbitration circuit 15 A backup power supply 7 is provided for backing up data, and refresh signals S ₅ and S ₁₀ output from the switching unit 19 and the refresh signal generating means 21 are input to the volatile memory 12 for refreshing.

(Operation)

And refresh enable signals S ₁ that is output from the refresh timing signal generating circuit 13 during the refresh enable, arbitration by the memory select signal Sse arbitration circuit 15 that outputs than this by entering the address signal S ₂ from the processor 3 to the memory select part 14 is, the refresh timing signal S ₃ is output at which is input to the refresh signal generating means 21, which from the refresh signal S _5, S ₆
Is output. Refresh signal S ₆ obtained from this unit 21 is output as the refresh signal S ₁₀ from the switching unit 19, the data is volatile memory 12 is refreshed by refresh signals S ₅ output as the refresh signal S ₁₀ from the unit 21 Will be held.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the outline of the configuration of an embodiment of the method and apparatus of the present invention, and FIG. 2 is a block diagram showing the configuration in detail.

 First, the configuration of the present embodiment will be described.

Data retention in the present embodiment is realized by the configuration as shown in the first and second drawings.

The microprocessor 3 controls the microprocessor peripheral unit 2 according to the timing of the oscillator 1. The reference and update of the volatile memory 12 from the microprocessor 3 are performed through the memory control unit 11.

13 volatile memory 12 is a frequency divider for generating a refresh enable signals S ₁ by dividing the output of the oscillator 1 'to cycle required for refreshing, 14 address signals generated in the processor 3 at the start access the address signal S ₂ enter the S ₂ is a memory select part for outputting a memory select signal Sse when the signal points to the volatile memory 12.

15 when the input of the memory select signal Sse arbitrates them, type refresh enable signals S ₁ and the memory select signal Sse outputs memory select signal Sse as the refresh timing signal S _3, when the input of the refresh enable signals S ₁ is a arbitration circuit for outputting a refresh cycle signal S ₇ that outputs a refresh enable signals S ₁ and the switching signal S ₈ refresh timing signal S _3, and the microprocessor 3 shows the in refresh cycle.

19 when the signal S ₈ switching from the arbitration circuit 15 is not input outputs the refresh timing signal S ₃ as a column address strobe signal S ₁₀ to the nonvolatile memory 12, when the switching signal S ₈ is input it is a switching unit for outputting the output signal S ₆ of the later explained third delay element 18 as a column address strobe signal S _10.

16 the first delay element for outputting a refresh timing signal S ₃ of the delayed predetermined time address switching signal S ₄ that is output from the arbiter circuit 15, a predetermined time an address switching signal S ₄ that is output from the first delay element 16 is 17 the second delay element for outputting the volatile memory 12 as the row address strobe signal S ₅ with a delay, 18 refresh signal a row address strobe signal S ₅ for output from the second delay element 17 delayed a predetermined time
A third delay element for outputting the S ₆ to switching unit 19.

20 is an address switching signal S ₄ output from the first delay element 16
An address signal inputted to S ₂ address switching signal S ₄ by the column address signal S _2, which is the address switcher is switched to a row address signal S ₉ and outputs the volatile memory 12.

7, a backup power supply for backing up the volatile memory 12, the frequency divider 13, and the arbitration circuit 15, and 6 a main power supply.

The memory control unit 11 includes a frequency divider 13, a memory selection unit 14, an arbitration circuit 15, a refresh signal generation unit 21 including a first to a third delay element 16 to 18, a switching unit 19, an address switching unit 20, and FIG. The memory input / output control unit and the power control unit are not shown.

Next, the operation of the present embodiment will be described with reference to the timing chart of FIG.

First, an operation in which the microprocessor 3 accesses the volatile memory 12 will be described.

The microprocessor 3 by the address signal S ₂ is generated when starting the access. The address signal S ₂ is input to the memory select part 14 and the address switching unit 20. Memory select part 14, the address signal S ₂ input volatile memory
When the address indicates 12, the memory selection unit Sse is output to the arbitration circuit 15. Arbitration circuit 15 arbitrates the memory select signal Sse is output at the refresh enable signals S ₁ and the memory select part 14 to output from the frequency divider 13, and for input of a memory select signal Sse switching a first delay element 16 the memory select signal Sse to section 19, and outputs it as the refresh timing signal S _3. The output of the switching signal S ₈ and the refresh cycle signal S ₇ does not change. Since switching portion 19 is switching signal S ₈ is not input, and outputs the refresh timing signal S ₃ as a column address strobe signal S ₁₀ to the volatile memory 12.

The first delay element 16 outputs an address switching signal S ₄ obtained by delaying the refresh timing signal S ₃ fixed time to a second delay element 17 and the address switching unit 20. The address switching section 20 outputs the address signal S ₂ by the address switching signal S ₄ from the first delay element 16 is switched from the column address signal to the row address signal to the volatile memory 12. S ₉ columns that output from the address switching unit 20, a row address signal.

The second delay element 17 outputs the volatile memory 12 and the third delay element 18 as a row address strobe signal S ₅ by delaying an address switching signal S ₄ that is output from the first delay element 16 fixed time.

The third delay element 18 delays the row address strobe signal S ₅ that is outputted from the second delay element 17 a certain time, to make a refresh signal S _6, but output to the switching unit 19, so when accessing refresh from switching portion 19 does not output the column address strobe signal S ₁₀ of use.

In this manner, the address is input in a time-division manner because the volatile memory 12 has an address input in order to make the external dimensions small.
This is due to time sharing. Reference and update of data are performed by the memory input / output control unit in the same manner as in the related art.

Next, an operation of refreshing the contents of the volatile memory 12 will be described. Refresh memory includes a column address strobe signal S _11, by interchanging the timing of the row address strobe signal S _5, it is realized.

The refresh enable signal S ₁ is generated by dividing the output of the oscillator 1 ′ by the frequency divider 13 to a period in which the volatile memory 12 needs to be refreshed. Since the frequency-divided signal is not directly related to the operation of the microprocessor 3, the same oscillator 1 'as the oscillator 1 may be used to reduce the cost. Refresh enable signals S _1, made by the frequency divider 13 is input to the arbitration circuit 15. The arbitration circuit 15 receives this input and determines whether or not there is access from the microprocessor 3 through the memory select unit 14. When there is an access from the microprocessor 3, the process waits until the access is completed. When there is no access, the arbitration circuit 15 immediately sends the switching signal S ₈ to the switching unit 19 as it is.
And indicates that a refresh cycle is being performed. Outputs a refresh cycle signal S ₇ to the microprocessor 3. And it outputs the refresh timing signal S ₃ to the first delay element 16 and switching unit 19 at the same time.

When the microprocessor 3 has a refresh cycle signal S ₇ from the arbitration circuit 15 is input, a refresh, to avoid memory access contention, the access of the memory is not performed until the refresh cycle signal S ₇ is eliminated.

The first delay element 16 receives the refresh timing signal S ₃ from the arbitration circuit 15, delays the signal S ₃ fixed time, and outputs the address switching device 20 and the second delay element 17.
Address switching unit 20 switches the address to be input to the volatile memory 12 by the address switch signal S ₄ that is output from the first delay element 16.

The second delay element 17 receives an address switching signal S ₄ that is output from the first delay element 16, delays the signal S ₄ fixed time,
Outputting as a row address strobe signal S ₅ in the volatile memory 12 and the third delay element 18.

The third delay element 18 outputs the switching portion 19 to the row address strobe signal S ₅ that is outputted from the second delay element 17 as the refresh signal S ₆ delayed a predetermined time. Since the switching signal S ₈ is input from the arbitration circuit 15, the switching unit 19 converts the refresh signal S ₆ output from the third delay element 18 into the volatile memory 12 as a refresh column address strobe signal S _10. Output. At this time, already volatile memory 12 as the row address strobe signal S ₅ is noted above because it is input to the volatile memory 12 is a refresh mode, the column address strobe signal S ₁₀ and the row address strobe signal S ₅ The data in the memory 12 is automatically refreshed by changing the timing.

〔The invention's effect〕

According to the present invention as described above, the refresh request from the circuit 13 for generating a refresh enable signals S ₁ when the refresh enable a refresh operation is necessary volatile memory 12 for storing and holding, the access from the processor 3 automatically generating a refresh signal S _5, S ₁₀ by the circuit 15 that arbitrates, the generated refresh signal
The volatile memory 12 is automatically refreshed by inputting S ₅ and S ₁₀ to the volatile memory 12, and the volatile memory 12, the refresh timing generation circuit 13 and the arbitration circuit 1
5 is backed up by the backup power supply 7 to retain the contents of the volatile memory 12 irrespective of the state of the main power supply 6. The memory is replaced by a relatively inexpensive and small volatile memory 12, and a circuit for refreshing the volatile memory 12 is provided by an inexpensive and simple refresh timing signal generation circuit 13, a memory select unit 14, an arbitration circuit 15, and a delay element. With the refresh signal generating means 21 and the switching unit 19, not only can the entire device requiring data retention in a large-capacity memory be inexpensive and small, but also a refresh timing signal generating circuit 13 and an adjustment unit can be provided in addition to the volatile memory 12. Since only the circuit 15 is backed up, there is an effect that power consumption can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the outline of the configuration of an embodiment of the method and apparatus of the present invention, FIG. 2 is a block diagram showing the configuration in detail, and FIG. 3 is a diagram for explaining the operation of this embodiment. FIG. 4 is a block diagram showing an outline of an example of a conventional method and apparatus, and FIG. 5 is a block diagram showing the configuration in detail. 3 ... (micro) processor, 6 ... main power supply, 7 ...
Backup power supply, 12 volatile memory, 13 refresh timing signal generation circuit (frequency divider), 14 memory select unit, 15 arbitration circuit, 16 first delay element,
17 second delay element, 18 third delay element, 19 switching section, 21 refresh signal generation means, S ₁ refresh enable signal, S ₂ address signal, Sse memory select Signal, S ₃ … refresh timing signal, S ₄ … address switching signal, S ₅ … refresh signal (row address strobe signal), S ₆ … refresh signal, S ₇ … refresh cycle signal, S ₈ … Switching signal, S ₉ ... Column, row address signal, S ₁₀ ... Refresh signal (column address strobe signal).

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-225968 (JP, A) JP-A-63-64532 (JP, A) JP-A-1-116994 (JP, A)

Claims (3)

(57) [Claims] 1. A refresh timing signal generating circuit (13) which inputs a timing signal which is a reference when refreshing a volatile memory (12) to a refresh timing signal generating circuit (13), and outputs a refresh enable signal (S ₁ ) from the processor at the start of access. The address signal (S ₂ ) from (3) is input to the memory select section (14), and the memory select signal (Sse) output from the address signal (S ₂ ) is arbitrated by the arbitration circuit (15), and the refresh enable signal (S ₁ ) or The refresh timing signal (S ₃ ) output from the circuit (15) when the memory select signal (Sse) is input is delayed by the refresh signal generating means (21) using a delay element to refresh the refresh signals (S ₅ , S _6). ) taken out, and the refresh timing signal outputted by the arbitration circuit (15) (S _3), the refresh signal generating means (21 More resulting refresh signal (S ₆₎ and switching output a switching unit (19), the refresh signal obtained from the switching section (S ₁₀₎ and the refresh signal generating means (21) a refresh signal obtained from (S ₅₎
Is input to the volatile memory (12), the volatile memory (12) is automatically refreshed, and the volatile memory (12) and the refresh timing generation circuit (13)
A volatile memory characterized by retaining the contents of the volatile memory (12) irrespective of the state of the main power supply (6) by backing up the arbitration circuit (15) with a backup power supply (7). Data retention method for large-capacity memory. 2. A circuit (13) for generating a refresh enable signal (S ₁ ) by inputting a timing signal serving as a reference when refreshing a volatile memory (12), a refresh enable signal (S ₁ ) and a processor The address signal (S ₂ ) from (3) is input to the memory select section (14), the memory select signal (Sse) output from the address signal is arbitrated, the refresh timing signal (S ₃ ) used at the time of refresh enable and switching are performed. signal circuit (15) for outputting (S _8), the refresh signal (S _5, to perform a refresh input to the volatile memory refresh timing signal outputted from the (S ₃₎ the arbitration circuit (15) (12) S ₆ ) A refresh signal generating means (21) using a delay element for outputting a signal, and a refresh timing signal (11) output from an arbitration circuit (15). And S _3), a refresh signal obtained from the refresh signal generating means (21) (switching portion (19 to S ₆₎ the switching output), volatile memory (12), the refresh timing generating circuit (13) and arbitration circuits ( includes a backup power source for backing up 15) (7), the refresh is input to switching unit (19) and the refresh signal generating means (refresh signal output from the 21) (S _5, S ₁₀₎ a volatile memory (12) A data storage device for a large-capacity memory using a volatile memory. 3. A circuit (13) for generating a refresh enable signal (S ₁ ) by inputting a timing signal which is a reference when refreshing a volatile memory (12), and a processor (3) generated at the start of access. memory select part for outputting a memory selection signal (Sse) when the address signal (S ₂₎ receives a signal corresponding address signal (S ₂₎ is pointing to the volatile memory (12) and (14), the memory selection signal ( Sse) and the refresh enable signal (S ₁ ) are input and arbitrated, and the memory select signal (Ss
Input memory select signal e) (outputs Sse) as a refresh timing signal (S _3), the refresh enable signal (S ₁ input at the time of refresh enable signal) (S ₁₎ refresh timing signal (S ₃ a) a switching signal and the arbitration circuit outputs a (S _8), and outputs the refresh cycle signal indicating that the refresh cycle (S ₇₎ to the processor (3) (15), the arbitration circuit (1
When the switching signal (S ₈ ) is not input from 5), the refresh timing signal (S ₃ ) is output to the volatile memory (12) as the column address strobe signal (S ₁₀ ), and the switching signal (S ₈ ) When input, the third delay element (18) described later
A switching unit (19) that outputs a refresh signal (S ₆ ) output from the switching unit as a column address strobe signal (S ₁₀ ), and a refresh timing signal (S ₃ ) output from the arbitration circuit (15) is delayed by a fixed time to switch addresses. an address switching unit first delay element outputs (20) (16) as the signal, the first delay element (16) is output from the address switching signal (S ₄₎ for a predetermined time delay in row address strobe signal (S ₅ ) And a row address strobe signal (S ₅ ) output from the second delay element (17) to the volatile memory (12) and a refresh signal (S ₆ ) by delaying the row address strobe signal (S ₅ ) for a predetermined time. A third delay element (18) for outputting to the switching unit (19) as a backup power supply for backing up the volatile memory (12), the refresh timing signal generation circuit (13) and the arbitration circuit (15). A large-capacity memory data holding device using a volatile memory comprising a source (7).