JPS62134896A - Memory control system - Google Patents

Abstract

PURPOSE:To prevent a refresh request and an access request from contending with each other in the same memory unit by controlling multiplexers of respective memory units which switch a refresh address and a data access address. CONSTITUTION:Mutually independent memory units 8 and 9 of a memory device 10 are accessed through multiplexers 6 and 7 which select and output refresh addresses from a refresh counter 3 and a refresh address counter 4 and a data access address from a microprocessor unit 2. Those multiplexers 6 and 7 are controlled by a memory control part 5 and when either of the units 8 and 9 is refreshed, the other had its data accesses, thereby preventing a refresh request and a data access request from contending with each other in one memory unit.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a data processing device having a memory device.

In particular, refresh requests for memory devices.

This is useful for reducing contention between access requests and access requests.

This invention relates to a suitable refresher control method.

[Background of the invention]

The conventional method is disclosed in Japanese Patent Application Laid-Open No. 171788/1988.

Data access requests and referrals as described.

The refresher operation is terminated due to conflicting requests.

By waiting for data access until the end of the process.

In order to avoid a decrease in processing performance, a microinstruction was provided to output a refresher request when executing an instruction that did not have a data access request, and the refresher operation was performed when the microinstruction was busy. However, in reality, there are many types of software, and it becomes necessary to add useless scripts to the software.

[Purpose of the invention]

An object of the present invention is to divide a memory device into independently accessible units, and when a certain unit of memory is being accessed,
Memory reflation of other units.

Request a refresh by opening the door.

Provides fewer conflicts with access requests.

There are many things.

[Summary of the Invention] 5 Dynamic memory retains memory contents.

Is it necessary to perform refresh operations periodically?

and glue flakes for the refresh operation.

Processing due to conflict between user requests and data access requests.

Various methods have been proposed as means to avoid the decline in performance.

It is.

In order to solve the above problems, the present invention provides a memory device.

Divide the location into multiple independently accessible units.

That is, there is only one address at a time for which a data access request is made, and it is for a certain unit of the memory device divided into the plurality of units. Therefore, the memory of this Shisen unit can perform reflexive operation at the same time.

Focusing on the above, it is possible to avoid conflicts between refresh operations and data access for a certain unit of memory.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. .

FIG. 1 shows the entire structure of the present invention including the data processing device.

Shows body composition. 1 is the basic black of the data processing device.

It is a clock generator that generates a clock, and all controls (goods) are synchronized with this clock. .

The memory device 10 also includes an independently accessible memory device.

It consists of memories 8 and 9. Access to said independent.

Available memories 8 and 9 are each 256 K X i bi
The sixteen 1° memory elements of t have a capacity of 512 bytes, and the addressing for memories 8 and 9 is alternately allocated to 8 and 9. Refresh counter 3
counts a certain period in order to refresh the memory device 10 at a certain period, and opens the refresh request door 13.
Output. Note that the above-mentioned constant period is 13 μs. Further, the 15 μs-P signal 14 is a haze signal when the reflex operation is not performed even after a certain period. The refresh request signal 13 and the data access request signal 18 from the MPU 2 are the refresh request signal 13.
and.

Process data access request 18 conflicts and memory.

Memo for controlling memories 8 and 9 in device 10.

When control signals 23 and 24 are supplied to the memory device 10.

The data is given to the memory control unit 15 of the roller. Memory device.

Memory addresses 25 and 26 supplied to device 10 are:

Where the address for fresh is generated.

A refresh address counter 4 is generated.

Address 15 and address 17° during data access are switched and supplied by multiplexers 6 and 7.

Next, the operation will be explained with reference to FIG. 1, FIG. 2 showing details of the memory control section 5, and FIG. 3 showing an operation timing chart of the present invention.

The refresh/noche counter 6 counts a fixed period of 13 μs and outputs a refresh request signal 16. The memory controller 5 latches the refresh request signal 13 into the flip-flop 42 at the trailing edge of the data access request signal 18. When the next data access request signal 18 is supplied, the .4.2 bit signal 43 of the address signal is determined, and if the bit is inactive, it is for data access.

Outputs the memory control signal 46 and outputs the memory 8 control signal 23
The rtAs1 signal 49, which is one of the signals, is output.

Ru. The other control signal, CA31 signal 51, is a memo.

is generated with reference to the control signal 46. Same as this.

At this time, a signal for refresh operation is outputted to the KRAS2 signal 5o. The following data access is required.

A request signal 18 is supplied. Software in general.

Since it operates sequentially, the 21-bit signal 43 of the address signal at the time of the data access request becomes active, and the memory control signal 47 for data access is outputted to the RA82 signal 50 in the same manner as described above. At this time, a signal for refresh operation is output to the simultaneous Kf (A81 signal 49).
The operation will be as per the state.

The flip-flop 28 is a logic that generates the reset signal 16 for the refresh counter 3, and the flip-flops 29, 50, and 31 are set to high level when the refresh operation is not completed even after 15 μI.

This is the logic of refreshing constraints. Implemented on Thursday.

According to the example, divided into independently accessible.

Memories 8 and 9 are in full operation, but the other is de.

- This is done at the same time as the data is being accessed.

riffs on data access operations in a single memory.

Ledges - actions do not conflict and are reflexive.

The processing power of a data processing device, depending on its operation.

It has the effect of not reducing the

〔Effect of the invention〕

O According to the present invention, when a certain unit of memory in a memory device having a plurality of independently accessible units of memory is accessed for data, it is possible to refresh other units of memory that are not accessed for data at the same time. This has the effect of avoiding contention between the refresher operation and the data access operation within the same unit.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of a memory control section, and FIG. 6 is a timing chart showing the operation of the present invention. 3... Refray! She counter, 4... refresh. Air address counter, 5... memory control unit, 8. . 9...Memory unit, 10...Memory device. +0

Claims (1)

[Claims] 1. A memory device configured with a dynamic memory, a refresh counter that outputs a refresh request to perform a refresh operation to the previous memory device at a constant cycle, and a memory device that processes conflicts between refresh requests and data access requests, and A refresh device comprising a memory control unit that controls the device, a refresh address counter that supplies a refresh address to the memory device, and a multiplexer that switches between supplying the refresh address and an address during data access to the memory device. A memory control method comprising: a memory device having a plurality of independently accessible memory units; and a multiplexer and a control unit for independently accessing the memory units.