JPS62207078A - Muting circuit - Google Patents

Abstract

PURPOSE:To facilitate the integration of the circuit, to reduce the cost and the circuit volume by providing a pattern matching circuit, the first and the second counters, and a control signal outputting circuit which execute the muting based on the discrete value of the counters. CONSTITUTION:The pattern matching circuit 103, when a chronizing separation signal B is inputted, outputs an output pulse shown by C in the figure in case when it judges that a normal horizontal synchronizing signal is present by measuring the width of the pulse. A horizontal free running circuit 101 is made operating in synchronization with the horizontal period of a composite video signal by the output 101 shown by C as long as the normal horizontal synchronizing signal 301 is present in the composite video signal, but outputs a self-reset pulse 110 shown by D to reset itself if the said output 110 lacks during a noise period 303 in order not to lose its synchronization with the horizontals period of the composite video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a muting circuit for a television set, and more particularly to an audio muting circuit using a digital circuit.

[Conventional technology]

A block diagram of an example of a conventional muting circuit is shown in FIG. In FIG. 2, 201 is a composite video signal, 202
is a synchronization separation circuit that inputs the composite video signal 2010, 206
is a synchronization separation signal, 204 is a bandpass filter into which the synchronization separation signal 206 is input, 205 is the output of the bandpass filter 204, 206 is an integration circuit, 207 is the output of the integration circuit 206, 208 is a control signal output section, and 209 is a control It is a signal output, and the arrow indicates the direction in which the signal travels.

In FIG. 2, when the composite video signal 201 is correctly input, the synchronization signal component is converted into the synchronization separation signal 206 by the synchronization separation circuit 202, and the fundamental frequency component of the synchronization separation signal 206 is 15.7I by the bandpass filter 204.
(Hz is extracted and its output 205 is sent to the integrating circuit 206
Control signal output unit 2 based on voltage output 207 smoothed by
08 is a control signal 2 indicating that it is okay to continue outputting audio.
Outputs 09. On the other hand, in Figure 2, if the reception condition deteriorates and the composite video signal 201 is not input correctly, the waveform of the synchronization separation signal 2060 will be distorted and the fundamental frequency will be 15.7.
Based on the fact that the potential of the output 207 of the integrating circuit 206 decreases because the KHz component decreases, the control signal output unit 20
8 outputs a control signal 209 for cutting off audio output.

[Problem that the invention seeks to solve]

However, in the example shown in FIG. 2, the bandpass filter 204 requires a coil and a capacitor, and the integrating circuit 206 requires a capacitor of several microfarads, which cannot be integrated into an IC, so the entire circuit must be constructed from individual components. In addition to high costs and mounting costs, the circuit volume is large, which hinders miniaturization of the device.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a low-cost, compact muting circuit.

[Means for solving problems]

The configuration of the present invention includes a pattern matching circuit that discriminates a horizontal synchronization signal from a synchronization separation signal of a composite video signal, a horizontal free-running circuit that operates in synchronization with the horizontal period of the composite video signal, and a self-resetting of the horizontal free-running circuit. A first counter that counts pulses and a second counter that counts the output of the pattern matching circuit.
, a reset signal is input to the first and second counters at the beginning of a specific period, and a control signal for muting execution is output based on the counted values of the first and second counters. It is characterized by having a signal output circuit.

〔Example〕

The present invention will be explained using examples. FIG. 1 is a block diagram of a muting circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a horizontal free-running circuit to which a clock, the output of a pattern matching circuit, and a self-reset pulse are input in order to operate in synchronization with the horizontal period of a composite video signal; 102;
106 is a first counter that is reset at the beginning of a specific period when a self-resetting pulse, which is the output of the horizontal free-running circuit 101, is input; horizontal free-running circuit 101 and a pattern matching circuit 10 that outputs to the second counter;
4 is a second counter 10 that is reset at the beginning of a specific period and counts the output of the pattern matching circuit 106;
5 is a control signal output circuit for outputting a control signal for muting execution based on the outputs of the first and second counters 102 and 104; 106 is for inputting to the horizontal free-running circuit 101 to operate the system of this circuit; , 107 is a clock input to the pattern matching circuit 106 to operate the circuit system, 108 is a synchronous separation signal,
109 is a self-resetting pulse which is the output of the horizontal free-running circuit; 110 is the output of the pattern matching circuit 106; 11
1 at the first and second counters 102.1 at the beginning of a particular period.
104 is the reset signal, 112 and 116 are the outputs of the first and second counters 102 and 104, respectively;
Reference numeral 114 indicates the control signal output of the control signal output circuit 105, and the arrow indicates the direction in which the signal advances.The digital synchronous signal processing system includes the pattern matching circuit 106 and the horizontal free-running circuit 101 shown in FIG. In this case, it can be used in the muting circuit of the present invention.

The operations of the pattern matching circuit 103 and horizontal free-running circuit 101 shown in FIG. 1 will be explained using FIG. 3.

In FIG. 3, (A) is the composite video signal, (B) is the synchronization separation signal 108 in FIG. 1, (C) is the output 110 of the pattern matching circuit 106 in FIG. 5 is a timing chart showing an output 109 of the horizontal free-running circuit 101. FIG. In FIG. 3, 301 is a horizontal synchronizing signal in the composite video signal, 602 is a luminance signal, and 606 is a period in which the horizontal synchronizing signal and the luminance signal disappear due to noise.

In FIG. 3, the synchronization separation signal of (B) has a pulse at the horizontal synchronization signal 6010 of the composite video signal of (A), but the horizontal synchronization signal of the composite video signal of (A, ) disappears in the noise period 606. The pulse is missing because the

The pattern matching circuit 106 in FIG. 1 is shown in FIG. 3(B).
When a synchronization separation signal is input, if it is determined that a regular horizontal synchronization signal exists by measuring the pulse width, etc., the output shown by the pulse in FIG. 3(C) is performed. On the other hand, the horizontal free-running circuit 101 in FIG. 1 is synchronized with the horizontal period of the composite video signal by the output 110 of the pattern matching circuit in FIG. However, the noise period 606
If the pattern matching output 110 is missing in Figure 3 (
D) Self-resetting pulse 1 to reset its own circuit
10 so as not to lose synchronization with the horizontal period of the composite video signal.

FIG. 4 shows the first and second counters 102 of the embodiment of FIG.
．． 104 and a control signal output circuit 1050. FIG. In FIG. 4, the same numbers as in FIG. 1 indicate the same signals, 401 to 408 are 1/2 frequency dividers, and φ
is the clock input, Q is the output, R is the reset terminal,
409 constitutes a binary counter, and 409 is an AND, and frequency dividers 401 to 408 and an AND 409 form the first counter in FIG.
411 to 41 constitute the counter 102, and similarly, 411 to 41
The frequency divider of 8 and the AND of 419 constitute the second counter 104 in FIG. 1, and 420 and 421 are NOR circuits connected to form an R-S latch, and the control signal output circuit of FIG. Corresponds to 105.

In the circuit shown in Figure 4, a specific period is selected as one field of the NTSC system, and if the reset signal 111 is a vertical synchronization signal, if the reception condition is good and a regular synchronization separation signal is input, the vertical synchronization signal will be used. First frequency divider 401~
408. After 411 to 418 are reset, continue (
The pattern matching circuit 10 in Fig. 1 between one field
6's output 110 is about 26 with almost no loss
Since 0 pulses are input to the frequency divider 411, when the number of input pulses exceeds 196, the AND 419 outputs a pulse and makes the NOR circuit 4200 control signal output 114 high level. Self-reset pulse 10
Since 9 is hardly output, the output of AND 409 is at a low level.

On the other hand, when the reception condition is poor, the synchronization separation signal is disturbed and the first
In the pattern shown in the figure, when the output 110 of the matching circuit 103 is almost missing, if 196 or more self-resetting pulses 109 are input to the frequency divider 401 during one filter 3, the AND 409 outputs a pulse and the NOR circuit 420 The control signal output 114 of is set to low level, and at this time, the AND41
9 is a low level.

In this way, the circuit shown in Figure 4 outputs a high level as a control signal when a normal composite video signal is input and muting is not required, and when the composite video signal is disturbed and muting is to be performed. Muting execution can be controlled by outputting a low level. In addition, in the circuit shown in Fig. 4, the set values of the first and second counters are set to 1.
96 is close to the number of horizontal periods of one field in the NTS, C method, 262.5, so for example, once the muting state is set, the output 110 of the pattern matching circuit will exceed 196 in one field. Since the function has a hysteresis characteristic so that the muting state is maintained until a fairly good state is reached, the muting function is stabilized so that it cannot be turned on and off in a short period of time.

FIG. 5 is a circuit diagram showing that the frequency dividers 401 and 402 of FIG. 4 are reset by the output of the pattern matching circuit. In FIG. 5, the same numbers as in FIG. 4 indicate the same signals and elements, and 501 is an OR circuit. In FIG. 5, the frequency dividers 401 and 402 are reset by the output 110 of the pattern matching circuit in addition to the signal 111 output at the beginning of a specific period, so that the frequency dividers 401 and 402 are reset by the output 110 of the pattern matching circuit immediately after the self-resetting pulse 109. If there is an output 110, it is provided with a function to invalidate the self-reset pulse and determine that the horizontal synchronization signal is not lost. In this way, the specifications of the horizontal free-running circuit become more relaxed, making it easier to create a synchronous signal processing system including a muting circuit.

〔Effect of the invention〕

Since this circuit can be configured with a digital circuit, it is easy to integrate it into an IC, which not only reduces component costs and mounting costs, but also reduces the circuit volume, resulting in a small size and low price.

In addition, providing hysteresis characteristics stabilizes the functional characteristics, resulting in a high-performance circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a muting circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional muting circuit, and FIG. 3 shows (A) a synthesized video signal, (B) a synchronous separation signal, (C) is a timing chart showing the output of the pattern matching circuit, (D) is a timing chart showing the output of the horizontal free-running circuit, FIG. 4 is a circuit diagram showing the first and second counters and the control signal output circuit, and FIG. FIG. 5 is a circuit diagram of a modification section when a function is added to the circuit of FIG. 4. 101...Horizontal free-running circuit, 102...10th counter, 103...Pattern matching circuit, 104...
...Second counter, 105...Control signal output circuit, 109...
... Self-reset pulse, 110 ... Output of pattern matching circuit, 111 ... Reset signal, 112 ... Output of first counter, 113 ...
. . . Second counter output, 114 . . . Control signal output.

Claims (2)

[Claims] (1) A muting circuit that controls audio output using a control signal includes a pattern matching circuit that determines a horizontal synchronization signal from a synchronization separation signal of a composite video signal, and a horizontal self-running circuit that operates in synchronization with the horizontal period of the composite video signal. a first counter for counting self-resetting pulses of the horizontal free-running circuit, and a second counter for counting the output of the pattern matching circuit; First, a reset signal is input, and the first and second
A muting circuit comprising a control signal output circuit that outputs a control signal for muting execution based on a count value of a counter. (2) The muting circuit according to claim 1, wherein the specific period is a repeating cycle.