KR900006305Y1 - Horizontal and vertical synchronizing signal and field detecting circuit for video signal - Google Patents

Horizontal and vertical synchronizing signal and field detecting circuit for video signal Download PDF

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KR900006305Y1
KR900006305Y1 KR2019870010650U KR870010650U KR900006305Y1 KR 900006305 Y1 KR900006305 Y1 KR 900006305Y1 KR 2019870010650 U KR2019870010650 U KR 2019870010650U KR 870010650 U KR870010650 U KR 870010650U KR 900006305 Y1 KR900006305 Y1 KR 900006305Y1
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signal
horizontal
output
flip
flop
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KR2019870010650U
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KR890001742U (en
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이종호
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삼성전자 주식회사
안시환
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising
    • H04N5/08Separation of synchronising signals from picture signals
    • H04N5/10Separation of line synchronising signal from frame synchronising signal or vice versa

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

내용 없음.No content.

Description

영상신호의 수평 수직동기 신호 및 필드검출회로Horizontal vertical sync signal and field detection circuit of video signal

제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제2도는 제2필드시의 본 고안의 파형도.2 is a waveform diagram of the present invention at the time of the second field.

제3도는 제1필드시의 본 고안의 파형도이다.3 is a waveform diagram of the present invention at the time of the first field.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

IC1,IC2 : 단안정 멀티바이브레이터 IC3,IC4 : 플립플롭IC1, IC2: Monostable Multivibrator IC3, IC4: Flip-Flop

본 고안은 영상합성(Video Composite)신호로부터 수평, 수직동기신호 및 필드검출신호를 발생시키는 회로에 관한 것이다.The present invention relates to a circuit for generating horizontal and vertical synchronization signals and field detection signals from video composite signals.

모니터나 텔레비젼 등의 영상합성신호는 필드별로 그 파형이 다르게 되는데, 종래에는 실용신안공보 제831호(디지탈 텔레비젼의 필드검출회로)에 나타난 바와같이 제1필드(odd filed)가 시작되는 경우에는 수평동기 펄스앞에 있는 등화펄스에서부터 3H(H는 수평동기 펄스의 주기)까지는 6개의 펄스가 발생되고, 제2필드(even field)가 시작하는 경우에는 7개의 펄스가 발생되므로 이 펄스를 카운팅하여 필드를 구별하도록 하였다.Image synthesized signals such as monitors and televisions have different waveforms for each field. Conventionally, as shown in Utility Model Publication No. 831 (Field Detection Circuit of Digital Television), when the first field (odd filed) starts, it is horizontal. Six pulses are generated from the equalization pulse before the sync pulse to 3H (H is the period of the horizontal sync pulse), and seven pulses are generated when the second field starts. To distinguish.

상기한 종래의 필드검출회로는 복잡할 뿐만 아니라 필드 검출신호는 수평동기신호를 적분회로를 통과하여 발생시키므로 오동작의 소지가 많을 뿐만 아니라 동기의 흐트러짐이 자주 생기는 단점과, 또한 필드검출신호 발생시 카운터를 사용하여 필드검출신호를 발생시키므로 회로가 복잡한 단점이 있었다.The conventional field detection circuit is not only complicated, but the field detection signal is generated by passing the horizontal synchronization signal through the integrating circuit, which causes a lot of malfunctions and frequently causes a disturbance of synchronization, and also generates a counter when the field detection signal is generated. The circuit is complicated because it generates a field detection signal.

본 고안은 상기한 재반 문제점을 해결하기 위하여 안출한 것으로서, 단안정 멀티바이브레터와 플립플롭을 이용하여 제1필드대와 제2필드때의 합성동기파형의 차이를 이용하여 수직동기신호, 수평동기신호, 필드검출신호를 발생시킬 수 있는 회로룰 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, using a monostable multivibrator and a flip-flop, using a vertical synchronization signal and a horizontal synchronization using the difference between the synthesized synchronization waveforms at the first field and the second field. It is an object of the present invention to provide a circuit capable of generating a signal and a field detection signal.

이하, 첨부된 도면에 의거하여 본 고안을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 고안의 영상신호의 수평, 수직동기신호 및 필드검출회로도를 나타낸 것으로서, 합성동기신호(A)가 단안정 멀티바이브레터(IC1)의 입력단자(A1)와 플립플롭(IC3, IC4)의 입력단자(D3, D4)에 인가되도록 연결하고, 단안정 멀티바이브레터(IC1)의 출력단자(Q1)를 단안정 멀티바이브레터(IC2)의 입력단자(B2)에 연결하며, 반전출력단자()는 검출된 수평동기신호를 출력함과 동시에 이 신호를 플립플롭(IC4)의 클럭단자(CK4)에 인가하고, 단안정 멀티바이브레터(IC2)의 반전출력단자()를 플립플롭(IC3)의 클럭단자(CK3)에 연결하며, 플립플롭(IC3, IC4)의 출력단자(Q3, Q4)에서는 수직동기신호 및 필드검출신호를 출력하도록 연결구성하였다.1 shows a horizontal, vertical synchronous signal and field detection circuit diagram of an image signal of the present invention, wherein the synthesized synchronous signal A is an input terminal A1 and flip-flops IC3 and IC4 of a monostable multivibrator IC1. Input terminal (D3, D4) of the terminal), and connects the output terminal (Q1) of the monostable multivibrator (IC1) to the input terminal (B2) of the monostable multivibrator (IC2), inverted output Terminals( Outputs the detected horizontal synchronizing signal and simultaneously applies the signal to the clock terminal CK4 of the flip-flop IC4 and outputs the inverted output terminal of the monostable multivibrator IC2. ) Is connected to the clock terminal CK3 of the flip-flop IC3, and the output terminals Q3 and Q4 of the flip-flop IC3 and IC4 are connected to output the vertical synchronization signal and the field detection signal.

상기한 단안정 멀티바이브레터(IC1, IC2)는 각각의 입력 단자(A1, A2)로 입력되는 펄스신호가 하이레벨에서 로우 레벨로 전환될 때 동작되거나 각각의 입력단자(B1, B2)로 입력되는 펄스신호가 로우레벨에서 하이레벨로 전환될때 동작하는 것으로서, 단안정 멀티바이브래터(IC1)의 클리어 단자(CLR)와 입력단자(B1), 또한 단안정 멀티바이브레터(IC2)의 클리어단자(CLR)와 출력단자(Q2)는 전원(Vcc)에 연결되어 있다.The monostable multivibrator IC1 or IC2 is operated when a pulse signal input to each input terminal A1 or A2 is switched from a high level to a low level or is input to each input terminal B1 or B2. It is operated when the pulse signal to be switched from the low level to the high level, and the clear terminal (CLR) and input terminal (B1) of the monostable multivibrator (IC1) and the clear terminal (1) of the monostable multivibrator (IC2). CLR) and output terminal Q2 are connected to the power supply Vcc.

상기한 구성을 갖는 본 고안의 회로 동작을 설명하면 다음과 같다.Referring to the circuit operation of the present invention having the above configuration is as follows.

합성동기신호의 수직동기신호 전후에는 수직동기신호를 항시 같은 형태로 하기 위한 등화펄스가 삽입되는데, 제2필드가 시작될 때에는 제2도의 파형도와 같이 7개의 펄스가 발생되고, 제1필드가 시작될 때에는 제3도의 파형도와 같이 6개의 펄스가 발생된다.Equalization pulses are inserted before and after the vertical synchronizing signal of the synthetic synchronizing signal to make the vertical synchronizing signal always the same shape.When the second field starts, seven pulses are generated as shown in the waveform diagram of FIG. 2, and when the first field starts. Six pulses are generated as shown in the waveform diagram of FIG.

단안정 멀티바이브레터(IC1)의 입력단자(A1)에 제2도 및 제3도의 A와 같은 합성동기신호가 입력되면 단안정 멀티바이브레터(IC1)는 반전출력단자(Q1)를 통하여 제2도 및 제3도 B와 같은 수평동기신호를 발생한다. 상기 수평동기신호가 반전된 단안정 멀티바이브레터(IC1)의 출력(Q1)파형은 다른 단안정 멀티바이브레터(IC2)의 입력단자(B2)에 인가되므로, 단안정 멀티바이브레터(IC2)는 제2도 및 제3도의 C와 같은 파형을 출력한다.When a synthetic synchronous signal such as A in FIGS. 2 and 3 is input to the input terminal A1 of the monostable multivibrator IC1, the monostable multivibrator IC1 is connected to the second through the inverted output terminal Q1. And a horizontal synchronous signal as shown in FIG. Since the output (Q1) waveform of the monostable multivibrator (IC1) in which the horizontal synchronous signal is inverted is applied to the input terminal (B2) of the other monostable multivibrator (IC2), the monostable multivibrator (IC2) Waveforms such as C in FIGS. 2 and 3 are output.

따라서, 플립플롭(IC4)은 클럭단자(CK4)에 상기 수평동기 신호가 인가되고, 입력단자(D4)에는 제2도 및 제3도의 A의 합성동기신호가 인가되는데, 플립플롭(IC4)은 클럭신호의 상승에지에서 입력단(D4)에 인가되는 신호가 출력단을 통하여 바로 출력되므로 제2도 및 제3도 (D)와 같은 파형이 출력된다. 즉, 제2도의 지점 "a"와 제3도의 지점 "d"에서 플립플롭(IC4)의 출력단(Q4)을 통하여 로우레벨의 출력되어 제2도 및 제3도 D와 같은 파형의 수직동기 신호가 출력되게 된다.Accordingly, in the flip-flop IC4, the horizontal synchronization signal is applied to the clock terminal CK4, and the synthesized synchronization signal of A of FIGS. 2 and 3 is applied to the input terminal D4, and the flip-flop IC4 is applied to the flip-flop IC4. Since the signal applied to the input terminal D4 at the rising edge of the clock signal is output directly through the output terminal, waveforms as shown in FIGS. 2 and 3 are output. That is, at the point "a" of FIG. 2 and the point "d" of FIG. 3, the low level is output through the output terminal Q4 of the flip-flop IC4, and the vertical synchronous signal of the waveforms of FIG. 2 and FIG. Will be output.

또한, 플립플롭(IC3)는 클럭단자(CK3)에 단안정 멀티바이브레터(IC2)의 반전출력()이 인가되고, 입력단(D3)에는 합성동기신호가 인가되는데, 이 플립플롭(IC3)도 상기의 플립플롭(IC4)과 동일하게 동작하므로 제2도 및 제3도 E와 같은 필드 검출신호가 출력되게 된다.In addition, the flip-flop IC3 has an inverted output of the monostable multivibrator IC2 at the clock terminal CK3. Is applied, and a synthetic synchronous signal is applied to the input terminal D3. Since the flip-flop IC3 also operates in the same manner as the flip-flop IC4, field detection signals such as FIG. 2 and FIG. Will be output.

이때, 제 필드의 경우에 "b"지점에서 필드검출신호가 로우레벨이 되어야하나, 플립플롭(IC4)의 출력신호인 로우레벨의 수직동기신호가 플립플롭(IC3)의 프리세트단자(Preset)에 인가되어 플립플롭(IC3)이 지점 "b"에서 프리세트되므로 제2필드에서는 제2도 (E)와 같이 필드검출신호는 하이레벨을 유지하게 된다.In this case, in the case of the field, the field detection signal should be at the low level, but the low level vertical synchronization signal which is the output signal of the flip-flop IC4 is the preset terminal of the flip-flop IC3. Since the flip-flop IC3 is applied at the point " b ", the field detection signal maintains the high level in the second field as shown in FIG.

한편, 제1필드의 지점 "c"에서는 플립플롭(IC3)의 클럭단자(CK3)하이레벨의 클럭신호가 인가될 때 입력단(D3)에 로우레벨의 신호가 인가되어 출력단(Q3)에 로우레벨의 제3도(E)와 같은 필드검출신호가 출력되는데, "d"지점에서 수직동기신호가 로우레벨로 되어 플립플롭(IC3)이 상기와 마찬가지로 프리세트되므로 필드검출신호는 다시 하이레베도 된다.On the other hand, at the point "c" of the first field, when the clock signal of the high level of the clock terminal CK3 of the flip-flop IC3 is applied, a low level signal is applied to the input terminal D3 so that the low level is applied to the output terminal Q3. A field detection signal as shown in Fig. 3E is outputted. At the point " d ", the vertical synchronization signal becomes low level and the flip-flop IC3 is preset as above, so the field detection signal is again high level. .

그러므로, 본 고안의 회로에 합성동기신호가 인가될때, 제1필드 및 제2필드에서 제3도 및 제2도와 같이 수평동기신호 및 수직동기신호가 검출될 뿐만 아니라 제1필드에서는 제3도(e)에서와 같이 제1필드를 알리는 파형이 출력되므로 제1필드 및 제2필드를 검출할 수 있게 된다.Therefore, when the synthetic synchronous signal is applied to the circuit of the present invention, not only the horizontal synchronous signal and the vertical synchronous signal are detected in the first field and the second field as shown in FIGS. 3 and 2, but also in the first field. As in e), the waveform informing of the first field is output, so that the first field and the second field can be detected.

상기한 바와 같은 본 고안에 의하면, 수직동기신호와 수평동기신호 및 필드검출신호를 단안정 멀티바이브레터와 플립플롭을 통하여 디지탈적인 방법을 사용하므로써, 종래의 아나로그적인 검출방법보다 정확성이 높아지며 또한 집적회로를 사용하므로써 간단하게 구성할 수 있는 이점이 있다.According to the present invention as described above, by using the digital method through the mono-stable multi-vibrator and flip-flop the vertical synchronization signal, horizontal synchronization signal and field detection signal, the accuracy is higher than the conventional analog detection method The advantage of simple configuration is the use of integrated circuits.

Claims (1)

합성동기신호(A)를 입력신호(A1)로 하여 합성동기신호(A)의 하강애지에서 반전출력단자(Q1)를 통하여 수평동기신호(B)를 출력하는 단안정 멀티바이브레터(IC1)와, 상기 단안정 멀티바이브레터(IC1)의 출력(Q1)을 입력신호(B2)로 하여 입력신호의 상승에지에서 반전출력단자(Q2)를 통하여 펄스신호(C)를 출력하는 단안정 멀티바이브레터(IC2)와, 상기 단안정 멀티바이브레터(IC1)의 출력신호인 수평 동기신호를 클럭신호(CK4)로 하고, 상기 합성동기신호(A)를 입력신호(D4)로 하여 수직동기신호(D)를 출력하는 플립플롭(IC4)과, 상기 단안정 멀티바이브레터(IC2)의 출력단(Q2)에서 출력되는 펄스(C)를 클럭신호(CK3)로 하고, 상기 합성동기신호(A)를 입력신호(D3)로 하며, 상기 플립플롭(IC4)에서 출력되는 수직동기신호(D)에 의해 프리세트되어 필드 검출신호(E)를 출력하는 플립플롭(IC3)으로 구성되는 것을 특징으로 하는 영상신호의 수평 수직동기신호 및 필드 검출회로.A monostable multi-vibrator (IC1) for outputting the horizontal synchronizing signal (B) through the inversion output terminal (Q1) at the falling edge of the synthetic synchronizing signal (A) using the synthetic synchronizing signal (A) as an input signal (A1) and And outputting the pulse signal C through the inverted output terminal Q2 at the rising edge of the input signal using the output Q1 of the monostable multivibrator IC1 as the input signal B2. A vertical synchronizing signal D using the IC2 and the horizontal synchronizing signal which is an output signal of the monostable multivibrator IC1 as the clock signal CK4 and the synthesizing synchronizing signal A as the input signal D4. Is a clock signal CK3, and the composite synchronous signal A is inputted as a flip-flop IC4 for outputting ") and a pulse C output from the output terminal Q2 of the monostable multivibrator IC2. A flip that is a signal D3 and is preset by the vertical synchronization signal D output from the flip-flop IC4 and outputs a field detection signal E Rob horizontal and vertical synchronization of the video signal being configured to (IC3) signal and a field detection circuit.
KR2019870010650U 1987-06-30 1987-06-30 Horizontal and vertical synchronizing signal and field detecting circuit for video signal KR900006305Y1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100416317B1 (en) * 2000-12-14 2004-02-05 박갑열 Shoes Sterilizer with Ultraviolet lamp
KR100486338B1 (en) * 2001-11-23 2005-05-24 (주)웹비전21세기 Apparatus for drying shoes and its control method

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