JPS6489679A - Pll circuit for television synchronizing signal - Google Patents

Abstract

PURPOSE:To prevent a displayed picture from being distorted before a PLL draws it in by making the phase of the output of the frequency divider of the PLL circuit coincide with an input synchronizing signal within the period of no video. CONSTITUTION:A television synchronizing signal from an input terminal 1 is led to a vertical synchronizing separation circuit 11, and a vertical synchronizing signal is obtained. Next, timing good for resetting the counter value of the frequency divider 7 is generated by a phase reset period generator 12. An actual reset timing signal is generated by a phase reset signal generator 13 based on the output of the phase reset period generator 12 and the input synchronizing signal. When a phase reset signal is outputted from this phase reset signal generator 13, the counter value of the frequency divider 7 is set at the reset phase value from a reset phase value input terminal 14. Thus, the phase of an output synchronizing signal can be reset at the desired phase against the input synchronizing signal.