JPS5471929A - Video signal level display method - Google Patents

Video signal level display method

Info

Publication number
JPS5471929A
JPS5471929A JP13917777A JP13917777A JPS5471929A JP S5471929 A JPS5471929 A JP S5471929A JP 13917777 A JP13917777 A JP 13917777A JP 13917777 A JP13917777 A JP 13917777A JP S5471929 A JPS5471929 A JP S5471929A
Authority
JP
Japan
Prior art keywords
video signal
terminal
inputted
output
signal level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13917777A
Other languages
Japanese (ja)
Inventor
Yasuo Yoshimura
Fumio Ukigaya
Masaharu Ooka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP13917777A priority Critical patent/JPS5471929A/en
Publication of JPS5471929A publication Critical patent/JPS5471929A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate the discrimination of video signal levels by converting an arbitrary video signal level to a dot signal and outputting it.
CONSTITUTION: A pulse train corresponding to the chrominance components width carrier wave and horizontal synchronizing signals are inputted to terminals 1 and 3 respectively and are supplied to FF 2 and 4 respectively, and the -Q output of FF 4 and the Q output of FF 2 are inputted to the reset terminal of FF 2 and NAND gate 5 respectively. Meanwhile, a video signal is inputted from terminal 6 and is supplied to the other input of NAND gate 5 through comparator 7, and the output of gate 5 is added to a video signal at terminal 6 to obtain a video signal including a dot signal at terminal 10. Now, FF 2 is operated as a frequency divider and outputs a pulse train, which has the half period of the chrominance components subcarrier, as a dot signal.
COPYRIGHT: (C)1979,JPO&Japio
JP13917777A 1977-11-18 1977-11-18 Video signal level display method Pending JPS5471929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13917777A JPS5471929A (en) 1977-11-18 1977-11-18 Video signal level display method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13917777A JPS5471929A (en) 1977-11-18 1977-11-18 Video signal level display method

Publications (1)

Publication Number Publication Date
JPS5471929A true JPS5471929A (en) 1979-06-08

Family

ID=15239355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13917777A Pending JPS5471929A (en) 1977-11-18 1977-11-18 Video signal level display method

Country Status (1)

Country Link
JP (1) JPS5471929A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752261A (en) * 1980-09-11 1982-03-27 Canon Inc Character processor
JPS59149471A (en) * 1983-02-15 1984-08-27 Mitsubishi Electric Corp Video camera

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752261A (en) * 1980-09-11 1982-03-27 Canon Inc Character processor
JPH0546133B2 (en) * 1980-09-11 1993-07-13 Canon Kk
JPS59149471A (en) * 1983-02-15 1984-08-27 Mitsubishi Electric Corp Video camera

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