JPH04144325A - Frame synchronizing device - Google Patents

Abstract

PURPOSE:To implement frame synchronization even without any loss of one frame by making the width of a frame clock obtained by frequency-dividing a clock synchronously with a transmission signal narrower than at least the width of a time slot of the transmission signal. CONSTITUTION:When the header of a shift data is detected by a header detection circuit 2 and a detection signal is outputted, a frame counting circuit 3 presets the counted valve to obtain a preset signal having the same pulse width as that of the header detection signal.A differentiation circuit 4 differentiates the preset signal for the time a half that of one time slot of a serial data to obtain a frame clock and to obtain parallel clock similarly. An S/P conversion circuit 5 sets a serial signal by using the rise of the parallel clock and converts the signal into a parallel data. Thus, after the detection of the frame header, the frame clock and the parallel clock whose rise is coincident with a header detection point of time are immediately obtained and frame synchronization is implemented without any loss of one frame.

Description

Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) The present invention relates to a frame synchronization device used in communication devices and the like.

(Prior Art) A conventional frame synchronization device used in a communication device is generally configured as shown in FIG. In FIG. 5, serial data is input to the data input terminal of the frequency register circuit 1, and a serial clock is input to the clock input terminal. The offset register circuit 1 shifts N-bit data (N is a positive integer), and the shifted input data is input to the header detection circuit 2.

The header detection circuit 2 detects the header of the transmission frame by decoding the frame data, and outputs a header detection signal to the frame counter 3.

The serial clock is input to the clock terminal of the frame counter 3, and this clock is frequency-divided to obtain a frame clock and a parallel clock.

Parallel clock is serial/parallel conversion (hereinafter referred to as S/
(denoted as P conversion) is manually input to one input terminal of the circuit 5.

The serial data is inputted to the other input terminal of the S/P conversion circuit 5, and the serial data is converted into parallel data based on the rise of the parallel clock.

FIG. 6 shows an example of the circuit shown in FIG.

Qa-Qh output (Qa.

Qd output (after inversion) is inputted to the AND circuit 2a, respectively. Ant circuit 2a constitutes header detection circuit 2,
Shift data can be obtained from the Qh output. AND circuit 2
The output of a is input to the preset terminal of the frame counter circuit 3, and the serial clock is input to the clock terminal. Further, the DO to D5 input terminals are pulled up via the resistor 3a, and the frame clock is obtained from the Q5 output.

The operation of the circuit shown in FIG. 5 will now be explained with reference to FIG.

In the figure, (1) is serial data manually input to the shift register circuit, (2) is a serial clock manually input to the shift register circuit 1 and frame counter circuit 3,
('3) is the header detection fr obtained by the header detection circuit 2.
No. j, (4) shows the fft data transferred by the fft register circuit 1, (5) shows the frame clock obtained by the frame counter circuit 3, and (6) shows the parallel clock output from the frame counter circuit 3. .

The input serial data is shifted by the number of pins of the header in the shift register circuit (see Figure 7 (4)).
reference). The shift data is detected as a header by the header detection circuit 2, and a header detection signal is obtained (see Fig. 7 (3) 5). The frame counter circuit '3 presets a count value using the header output signal and divides the frequency of the serial clock to obtain a frame clock and a parallel clock (see (5) and (6) in FIG. 7). S/P conversion circuit 5
The serial data is set by the rising edge of the parallel clock, and the serial data is converted to parallel data.

FIG. 8 shows another embodiment of the conventional frame synchronization device.

Parallel data is input manually to the input terminal of the header detection circuit 2. The header detection circuit 2 detects the header of the transmission frame and outputs a header detection signal to the frame counter 3.

The serial clock is input to the tally terminal of the frame counter 3, and this clock is frequency-divided to obtain a frame clock and a parallel clock.

Parallel clock is parallel/serial conversion (hereafter P
/S conversion) is manually input to one input terminal of the circuit 7.

The parallel data is input to the other input terminal of the P/S conversion circuit 7, and the serial clock is input to the clock terminal.

The P/S conversion circuit 7 reads the parallel data at the rising edge of the parallel clock and converts it into serial data by converting the data to serial data.

The operation shown in FIG. 8 will be further explained below.

The header detection circuit 2 exposes the header of the input parallel data and outputs a header detection signal to the frame counter circuit 3.

The frame counter circuit 3 has a count value preset by the header detection signal 1, and divides the serial clock to obtain a frame clock and a parallel clock.

The P/S conversion circuit 7 reads the parallel data at the rising edge of the parallel clock, shifts it, and converts it into a serial signal.

According to the operation described in section 2, when the counter circuit is in a free-running state,
In other words, if a frame header is detected when the output signals of the counter circuit (frame clock and parallel clock) are at "H" level, the output signal of the counter circuit may not change (Figure 7 (3), (5) reference). In such a case, since the "H" level of the frame clock exists before the header is detected, the transition point of the rising edge may not coincide with the beginning of the frame (when the header is detected).

Also, serial/parallel conversion or parallel/serial conversion is performed at the change point of the counter circuit output. Therefore, there is a problem in that whether a counter circuit output signal having a change point that coincides with the beginning of the transmission frame is obtained is frame delayed.

(Problems to be Solved by the Invention) As described above, the conventional frame synchronizer obtains the frame clock and the parallel clock by frequency-dividing the serial clock. Therefore, depending on the free-running state of the frame counter, there is a problem that there is a one-frame delay in obtaining the frame clock and parallel clock having a change point that coincides with the beginning of the transmitted frame after the frame header is detected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frame synchronization device that performs frame synchronization without losing a single frame.

[+14 features of the invention (Means for solving the problem) This invention comprises a frame clock obtained by frequency-dividing a clock synchronized with a transmission signal, which is made narrower than at least the width of a time slot of the transmission signal. It is.

(Function) According to the above arrangement, the pulse width of the frame clock and the parallel clock can be made shorter than the time slot of the serial signal. Therefore, it is possible to obtain a frame clock and a parallel clock synchronized with a frame without frame loss at the same time as header detection.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the invention.

The embodiment shown in FIG. 1 corresponds to the above-mentioned FIG. 5, and the same parts as in FIG. 5 will be described with the same reference numerals (t).

The difference from the previous FIG. 5 is that a differentiating circuit 4 is provided after the frame counter circuit 3. That is, the output of the frame counter circuit 3 is input to one input terminal of the differentiating circuit 4, and the header detection signal is input to the other input terminal. Further, the serial clock is input to one clock input terminal of the differentiating circuit 4, and the serial clock via the inverting buffer 6 is input to the other clock input terminal.

The differentiating circuit 4 outputs the pulse width of the frame clock and parallel clock as half of one time slot of serial data.

FIG. 2 shows an example of the circuit shown in FIG.

Qa-Qb output (Qa.

Qd outputs (after inversion) are respectively input to the AND circuit 2a. The AND circuit 2a constitutes a header detection circuit 2,
Shift data is obtained from the Qh output. The output of the AND circuit 2a is input to the preset terminal of the frame counter circuit 3, and the serial clock is input to the clock terminal. Further, the DO to D5 input terminals are pulled up via a resistor 3a. The output of the frame counter circuit 3 is
It is supplied to the differentiating circuit 4. Differential circuit 4 is AND circuit 4
a, 4 b, 4 c, 4 e-, D
It consists of seven lip-flops 4d and an OR circuit 4f. The QO to Q5 outputs of the frame counter circuit 3 are respectively input to an AND circuit 4a. AND circuit 4a
The output is input to one input terminal of the AND circuit 4b, and the other input terminal is supplied with a serial clock or a manual input. A frame clock signal 111 is output from the output of the AND circuit 4b. Also, the QO to Q2 outputs of the frame counter circuit 3 are supplied to the AND circuit 4c. The output of the inverting buffer 6 is connected to the clock terminal J' of the D flip-flop 4d.
be provided. The output of the AND circuit 4c is given to the D input terminal of the D flip-flop 4d, and also to the AND circuit 4e.
is supplied to one input end of the . The AND circuit 4e performs an AND operation on the output of the ant circuit 4c and the Q output of the D-fringe float sub 4d, and supplies the output to one input end of the OR circuit 4f. The OR circuit 4f performs an OR operation between the output of the AND-]〇- circuit 4e and the frame clock, and outputs a parallel clock.

The operation of the circuit shown in FIG. 1 will be explained below with reference to FIG.

In the figure, (1) is serial data input to the shift register circuit 1, (2) is a serial clock input to the shift register circuit] and the frame counter circuit 3,
(3) is the header detection signal obtained by the header detection circuit 2,
(4) shows the shift data shifted by the shift register circuit 1, (5) shows the frame clock obtained by the differentiating circuit 4, and (6) shows the parallel clock obtained by the differentiating circuit 4.

The input serial data is shifted by the number of bits of the header in the shift register circuit 1 (see figure lff13).
4)). The header of the shift data is detected by header detection circuit 2.
is detected, and a header detection signal is output (see FIG. 3 (3)). The frame counter circuit 3 obtains a preset signal whose count value is the same as the header detection signal, and a preset signal which sets the pulse width to the same value as the header detection signal.

The differentiating circuit 4 differentiates the preset signal by half of one time slot of the serial data to obtain a frame clock (see FIG. 3 (5)), and similarly obtains a parallel clock (the third
(see Figure (6)).

The S/P conversion circuit 5 sets a serial signal at the rising edge of the parallel clock and converts it into parallel data. According to this configuration, FIG. 3 (3), (5),
As shown in (6), after the frame header is detected, the frame clock and parallel clock whose rise coincides with the time of header detection are immediately obtained, and frame synchronization can be performed without losing a single frame. Note that the header detection signal may be directly introduced into the differentiating circuit 4, and the frame clock may be output by ANDing this and the serial clock.

FIG. 4 shows another embodiment of the invention.

The embodiment shown in FIG. 4 corresponds to the previous FIG. 8, and the same parts as those in FIG. 8 will be described with the same symbol -n.

The difference from the previous FIG. 8 is that a differentiating circuit 4 is provided after the frame counter circuit 3. That is, the output of the frame counter circuit 3 is input to one input terminal of the differentiating circuit 4, and the header detection signal is input to the other input terminal. Further, the serial clock is inputted to one clock input terminal of the differentiating circuit 4, and the serial clock via the inversion buffer 6 is inputted to the other clock input terminal.

The differentiating circuit 4 outputs the pulse width of the frame clock and parallel clock as half of one time slot of serial data.

The operation shown in FIG. 4 will be further explained below.

The header of the input parallel data is detected by the header detection circuit 2 to obtain a header detection signal. The frame counter circuit 3 presets a count value using the header detection signal to obtain a preset signal.

The differentiating circuit 4 differentiates the preset signal by half of one time slot of serial data to obtain a frame clock, and similarly obtains a parallel clock.

The differentiating circuit 4 may introduce a header detection signal, perform an AND operation on this signal and a serial clock, and output a frame clock.

The P/S conversion circuit 7 reads parallel data at the rising edge of the parallel clock, shifts it, and converts it into a serial signal.

Even in the above configuration, after detecting the frame header, it is possible to immediately obtain a frame clock and a parallel clock that are synchronized with the frame, and frame synchronization can be obtained without losing a single frame. Note that the pulse widths of the frame clock and parallel clock do not necessarily have to be half the time slot of the transmission signal, but may be narrower than the time slot.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a frame synchronization device that can perform frame synchronization without losing a single frame because the frame clock and parallel clock can be obtained immediately upon detection of the frame header. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a frame synchronization device according to the present invention;
2 is a diagram showing an example of the circuit shown in FIG. 1, FIG. 3 is a diagram for explaining the timing of the circuit shown in FIG. 1,
FIG. 4 is a diagram showing another embodiment of the present invention, FIG. 5 is a diagram showing a conventional frame synchronization device, FIG. 6 is a diagram showing an example of the circuit shown in FIG. 5, and FIG. 7 is a diagram showing an example of the circuit shown in FIG. FIG. 5 is a diagram for explaining the timing of the circuit shown in FIG. 5, and FIG. 8 is a diagram showing another example of the conventional frame synchronization device. 1... Shift register circuit, 2... Header detection circuit, 3... Frame counter circuit, 4... Differential circuit,
5... Serial/parallel conversion circuit, 6... Inversion buffer, 7... Parallel/serial conversion circuit. Applicant's representative Patent attorney Takehiko Suzue] 5 - Unexamined Japanese Patent Publication No. 4. -144325 (6)

Claims (3)

[Claims] (1) In a frame synchronization device having header detection means for detecting a frame header of a transmission signal, and frame counter means for dividing a clock synchronized with the transmission signal to generate a frame clock, the frame clock is set to at least the time of the transmission signal. A frame synchronizer characterized by having a width narrower than that of a slot. (2) A claim comprising: serial/parallel converting means for converting a serial signal into a parallel signal, wherein the parallel clock obtained from the frame counter means is at least narrower than the width of a time slot of the serial signal. The frame synchronization device according to item 1. (3) The invention further comprises a parallel/serial conversion means for converting a parallel signal into a serial signal, and the parallel clock obtained from the frame counter means is made narrower than at least the width of a time slot of the serial signal. The frame synchronization device according to item 1.