JPS60214661A - Detecting circuit for input absence signal - Google Patents

Abstract

PURPOSE:To control a synchronism protecting circuit so that a frame synchronism detection signal is generated unless there is a CMI input signal and eliminate the fruitless operation of a control circuit, etc., by providing the input absence signal detecting circuit to an interface circuit part. CONSTITUTION:The input absence signal detecting circuit 7 is interposed between the received signal input terminal RC111 of the interface circuit part 1' of an input absence signal detecting circuit and the synchronism protecting circuit 2. A clock signal M80KI is received by the counter 41 of this circuit 7 and inputted to one terminal of an AND gate 43, and a clock signal M160KI is inputted to the other terminal of the gate 43. Further, a CMI detecting circuit 42 receives a CMI input signal and outputs a differential signal at the fall of the signal 160KI. The counter 41 is cleared with the output signal of this circuit 42, and an FF circuit 44 is set with the output of the gate 43 and reset with a signal CNT from the circuit 42. Then, the NOT output Q' from the circuit 44 is applied to the circuit 2 as a synchronism protecting circuit control signal to eliminate the fruitless operation of the control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to digital transmission using CMI codes.
The present invention relates to an input no-signal detection circuit used for forming an interface.

(2) Prior art and problems FIG. 1 is a block circuit diagram of an interface circuit section 1 and various circuits related thereto. The interface circuit unit 1 includes a synchronization protection circuit 2, a frame assembly circuit 3, and a frame disassembly circuit 4, and performs code conversion, synchronization, transmission frame assembly and disassembly, and the like. A control circuit 6 controls these interface circuits.

In FIG. 2, the CMI signal is illustrated. C as shown
In the MI signal, the logic signal "0" is represented by a signal that changes from low level to high level ■ at the midpoint of the bit.
A logic signal "1" is represented by a signal that alternates between low and high. A specific example is shown in FIG. In other words, FIG. 3(1) shows the data displayed as a logic signal "0" or "l", FIG. 3(2) shows the NRZ signal corresponding to the data, and FIG. 3(3) shows the NRZ signal corresponding to the data. CMI signals corresponding to the data are written in parallel.

In addition to the above-mentioned signals, the CMI signal also includes violations (
A frame synchronization signal) is added for each frame of the signal. Biolage day is the logic “1” that appeared before it.
This is indicated by maintaining the same level as the signal for a period of one pit. The section indicated by the arrow in the CMI signal in FIG. 3 (4) indicates a violation.

In the circuit shown in Fig. 1, if the CMI signal is not input from the receiving side and the receiving input of the T-wire interface circuit section 1 is fixed to H or L, a violation is detected because the same level continues for more than 2 bit periods. Therefore, the synchronization detection signal of the synchronization protection circuit 2 rises. As a result, pseudo-synchronization is achieved, the data bus is assumed to be established, and data exchange begins, but the data bus is not actually established and no response signal indicating invalidity of the output data is returned. The control circuit, etc. performs unnecessary operations.

(3) Object of the Invention The object of the present invention is to solve the problems in the interface circuit section in digital transmission using the CMI code mentioned above, and based on the concept of providing an input no-signal detection circuit in the interface circuit section, the CMI The purpose is to prevent the frame synchronization detection signal from rising when there is no input signal (the two-synchronization hold circuit is fully controlled, and unnecessary operations such as the control cycle are eliminated).

(4) Structure of the Invention In the present invention, C'Ml signal? a CMI detection circuit that receives the CIvl I signal and outputs a signal obtained by differentiating the CIvl I signal;
The output signal of the detection circuit (cleared from 2) is a counter that counts the n1 clock signal and outputs the full output signal when the counted value reaches a certain predetermined value n, and receives the output signal from the counter and resets the output signal. An input no-signal detection circuit is provided which includes a flip-flop circuit received at an output set terminal of a CMI detection circuit and controls a synchronization protection circuit by the output of the flip-flop circuit.

(5) Embodiment of the Invention FIG. 4 is a block circuit diagram of an input no-signal detection circuit as an embodiment of the present invention, and FIG. 4 is a block circuit diagram of an interface circuit section 1' using the input no-signal detection circuit. This is shown in Figure 5. The human input no-signal detection circuit 7 is inserted between the received signal input (3) input terminal RCIII in the interface circuit section and the synchronization protection circuit 2.
,ru.

In FIG. 4, a counter (CT) 4i receives a clock signal M80KI' and counts. The output of counter 41 is supplied to one input terminal of AND gate 43. The clock signal M160 is connected to the other input terminal of the AND gate 43.
KI is added.

Clock signal M160KI has twice the frequency of clock signal M80KI. The CMI detection circuit 42 receives the CMI input signal and outputs a signal obtained by differentiating the signal at the falling edge of M160KI.

This output signal (CNT) clears the count value of the counter 41. The flip-flop circuit (FF) 44 receives the output (R8T) of the AND gate 43 at its reset terminal R, receives the output signal (CNT) of the CMI detection circuit 42 at its set input terminal S, and outputs its negative output (Q). It is supplied to the synchronization protection circuit 2 as a synchronization protection circuit control signal (C8).

Next, the operation of the above-mentioned circuit will be explained using the sixth waveform diagram. Figure 6 (1) shows the clock signal (4) Mf (160KI) or Figure 6 (2) (the second shows the clock signal Mf).
The waveform of K80KI is shown. @6 Figure (3) has a commercial
The I input signal is shown. The part where the code nature is violated in the CMI input input signal waveform is a violation.The output (CNT) of the OCMI detection circuit 42 corresponds to the falling part of the CM signal (=, Clock M160K
Is the waveform of the I signal (a two-synchronized waveform; Fig. 6 (5) to 7) the waveform of each digit when, for example, a 3-digit binary counter is used as the counter 41? Lower digit order (represented as CT-1, CT-2 and CT-3; 6th
The waveform diagrams in Figures (5) to 7) are for CNT in Figure 6 (4).
If there is no broken line signal in the signal and there is a CNT signal shown in the broken line, at that point CT-1,
All waveforms of CT-2 and CT-3 are L. FIG. 6(8) shows the waveform of the R8T signal. In this example, the R8T signal is obtained by the AND of CT-1, the negation of CT-2, CT-3, and the clock signal M160KI.
The predetermined count value is CT-1, CT
-2 and CT-3 can be selected in combination. When no CMI signal is input, the CMI detection circuit 42
Since the input of ) is constant, no CNT signal is output. Therefore, the counter 41 is not cleared and the integration continues until it reaches a predetermined value, and the R8T signal is output. R8T Hakugo is 7
When applied to the reset terminal of the lip-flop circuit 44, the output Q becomes H, and the synchronization protection circuit control signal (C8) is supplied to the synchronization protection circuit 2 as shown in FIG. 6(9). C
The synchronization protection circuit 2 receiving the 8 signal suppresses output of the frame synchronization detection signal (MSYN).

When the CMI double signal is input, the CMI detection circuit 42
The NT signal is output, the flip-flop circuit 44 is set, the output Q is set to L, and the MSY in the synchronization protection circuit 2 is set.
Release the N signal inhibition.

(6) Effects of the Invention According to the present invention, the synchronization protection circuit is controlled so that the frame synchronization detection signal does not rise when there is no CMI input signal,
By using the CMI code, unnecessary operations of the control circuit in digital transmission can be eliminated.

[Brief explanation of drawings]

Figure 1 is a diagram showing the outline of the interface circuit, Figure 2 is a diagram explaining the CMI signal, and Figure 3 is the diagram of the CMI signal.
A waveform diagram showing an example of an MI signal, FIG. 4 is a block circuit diagram showing an input no-signal detection circuit as an embodiment of the present invention,
FIG. 5 is a block diagram of an interface circuit section using the input no-signal detection circuit of FIG. 4, and FIG. 6 is a waveform diagram illustrating the operation of the circuit of FIG. 4. ], 1'... interface circuit section, 2...
... Synchronization protection circuit, 3 ... Frame assembly circuit, 4 ... Frame disassembly circuit, 6 ... Control circuit, 7 ... Input no signal detection Circuit, 41...
...Counter, 42...CMI detection circuit,
43... ant game, 44...7
Lipflop circuit.

Claims (1)

[Claims] In digital transmission using CMI codes. A CMI detection circuit that receives a CMI signal and outputs a signal obtained by differentiating the CMI signal, which is cleared by the output signal of the CMI detection circuit, counts clock signals, and outputs a signal when the counted value reaches a predetermined value. a counter that outputs T, and receives it at the output reset terminal of the counter,
An input no-signal detection circuit comprising a flip-flop circuit whose set terminal receives an output of the CMI detection circuit, and a synchronization protection circuit is controlled by the output of the flip-flop circuit.