JPS6013574B2 - Shift calculation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for counting pulses in a predetermined block of a digital communication system.

Conventionally, when counting, for example, error pulses existing in a predetermined block, arithmetic circuits corresponding to each block are provided to count the pulses.

An example of a conventional circuit is shown in FIG.

As shown in FIG. 1, consider the case where the signal sequence is M bits, one block is made up of K blocks, and one frame is made up of N bits, ie, M×K=N.

When performing an operation on a signal between one frame, such as counting the number of error signals "1" in a unit time to calculate the pulse error rate, first from 1 to N, then from M0 to M0 while shifting one block at a time. From 1 to M0N, then 2
An arithmetic circuit having the configuration shown in FIG. 2 is known for counting from M+1 to 2M+N.

Arithmetic units AC, AC2, ACK, whose number is equal to the number of blocks K forming one frame, and a delay device DL having a one-block delay time that connects them to each other.
, DL-, and memory circuits MM, , M corresponding to the arithmetic units
M2... MMK and general memory device M were required.

The present invention aims to improve the above-mentioned drawbacks and provide an arithmetic circuit with a simple configuration.

FIG. 3 is a block diagram showing a configuration for counting the number of "1" signals as an embodiment of the present invention, where SR is a shift register, in this case a shift register that shifts the number of bits in one frame by N stages; CP is a comparison circuit, AC is a first arithmetic unit, in this case a normal counter, AC2 is a second arithmetic unit, in this case an up/down counter, and M is a general memory device.

Now, when a serial 1-bit signal is applied in the same signal sequence as mentioned above, the first arithmetic unit AC counts the number of "1"s in the input signal ■K for one frame, and transfers that value to the second Set to computing unit AC2. For example, in the signal sequence shown in Figure 4, there is a ``1'' in one frame, so it is
Reset the base number to 0100. If the signal (2) is the current signal, the signal (2) is an input signal that has passed through the shift register, or in other words, it is a signal from one frame before. Signal ■ and ■
is compared at the comparison time CP, and if ■ is "1" and ■ is "0", the preset "1" is determined as shown in Figure 4 Comparison C for one frame before the corresponding bit of the signal. Since the number is greater than the number of In order to count down AC2, if ■ and ■ are equal (fourth
The comparator circuit CP sends a signal (2) that leaves the value of AC2 unchanged to the second arithmetic unit AC2. Note that the clock 1 is a clock pulse with a 1-bit rate, which causes the second arithmetic unit AC2 to repeat the above-described count-up or count-down operation for each bit. The output {circle around (2)} of the second arithmetic unit AC2 is input to the general memory device M, and is read out block by block using a clock pulse 2 at a block rate of 1 to obtain an output {circle around (2)}. In this way, the operation (counting the number of 1'') between one frame is performed by shifting one block at a time.If the input signal maintains the relationship of M×K:N, the signal If a more approximate calculation than that described above is acceptable, other shift amounts may be used, such as two blocks.

Although the case in which the signals of "1" are counted has been described above, it is also possible to perform other calculations by using an arithmetic unit other than a counter. In this way, according to the present invention, a zero arithmetic circuit can be configured with simple elements using only two arithmetic units and a memory device, and a desired arithmetic operation can be performed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an input signal format, FIG. 2 is a diagram showing an example of the configuration of a subordinate arithmetic circuit, FIG. 3 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 4 is a diagram showing an example of a signal. It is a figure explaining the situation to compare. ■... Input signal, ■... Signal passed through shift register, AC,... First arithmetic unit, AC2...
Second arithmetic unit, CP... Comparison circuit, SR...
Shift register, OM... General memory device. *1 figure false 4 figure Chi 2, Takiku 3 figure

Claims (1)

[Claims] 1. A first arithmetic unit to which an input signal is applied and performs an addition operation of an error signal of one frame section signal of the input signal, and a comparison circuit that compares the input signal that has passed through the shift register of one frame section and the original signal. , a second arithmetic unit to which the output of the first arithmetic unit is applied, the second arithmetic unit applies the output of the comparison circuit to the second arithmetic unit, and the second arithmetic unit applies the output of the comparison circuit to the output of the first arithmetic unit. A shift arithmetic circuit characterized in that it performs addition and subtraction operations and reads out the output of a second arithmetic unit every block of time for forming an input signal.