JPH0832426A - Non-signal detection circuit - Google Patents

Abstract

PURPOSE:To provide the non-signal detection circuit that outputs a non-signal detection signal in an accurate timing for a video signal or the like required for digital processing of the video signal in such a way that a synchronizing signal is generated in the inside of the circuit on the occurrence of a nonsignal. CONSTITUTION:The circuit is provided with a counter 2 counting pulses from an oscillator 1 oscillating continuous pulses of a prescribed period and cleared by an input pulse SO being a signal to be detected for the existence of the signal, and the counter 2 outputs the count when the input pulses are missed for a period regarded to be a non-signal or over. When the input pulses are missed over the period to be regarded as a non-signal state, since the counter 2 outputs an output signal S2, the non-signal is detected. An output S3 of a flip-flop 3 which is set by the signal S2 and reset by the input pulse SO indicates a consecutive non-signal detection signal.

Description

Detailed Description of the Invention

[0001]

[Industrial application] Plasma display (PDP)
The present invention relates to a no-signal detection circuit for a video signal or the like that is necessary when digitally processing a video signal, such as when a video signal is displayed, a synchronizing signal is internally generated when there is no signal.

[0002]

2. Description of the Related Art Conventionally, when determining the presence or absence of an input video signal, a sync signal separated from a composite video signal is CR.
An analog circuit was used, such as integrating in a circuit and making a determination based on the DC level after integration. In this case, the time required for no-signal detection varies due to factors such as variations in CR constants and temperature. For example, in the case of a PDP, a video signal processing circuit that internally requires a synchronization signal when a signal is interrupted is displayed on the screen. It may cause malfunctions such as flashing.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a no-signal detection circuit that does not vary in detection time and outputs at an accurate timing.

[0004]

A counter that counts pulses from an oscillator that oscillates continuous pulses of a constant cycle and clears the pulses with an external input pulse that is a detected signal indicating the presence or absence of a signal is used. As the value, a count value is set so that the count output is performed when the input pulse is missing for a period longer than a period considered as no signal.

[0005]

When the input pulse is missing more than the period considered to be the no signal state, the no signal can be detected by the output of the counter. Since this no-signal detection circuit is composed entirely of digital circuits, no-signal can be accurately detected within the predicted time.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A no-signal detection circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic block diagram of a first embodiment according to the present invention. 1 is a continuous pulse oscillator, 2 is a counter, and 3 is a flip-flop.
The counter 2 inputs the output S1 of the oscillator 1 which generates a pulse having a shorter cycle than the horizontal synchronizing signal S0 of the input video signal as a clock signal, and inputs the horizontal synchronizing signal S0 as the clear signal for the first period, and outputs it for a longer period than the period of the horizontal synchronizing signal S0. When continuously counting, the count output S2 is output. The flip-flop 3 is set by this output S2, cleared by the horizontal synchronizing signal S0, and outputs the no-signal detection output S3.

The counter 2 outputs the signal S2 after continuous counting for a period longer than the period of the horizontal synchronizing signal S0, that is, when the input signal is lost. Since the flip-flop 3 is set at S2 and reset by the horizontal synchronizing signal S0, that is, when there is a signal, the output S of the flip-flop 3 is
3 indicates no signal. In this way, since no signal can be detected digitally, it is possible to detect no signal without variation after it has become no signal.

FIG. 2 shows a second embodiment according to the present invention.
(A) is a schematic block diagram and (B) is a timing diagram of main pulse signals. 1 is a continuous pulse oscillator, 2 is a first
Counter, 4 is a second counter, and 3 is a flip-flop. The first counter 2 uses the output S1 of the oscillator 1 which generates a pulse having a shorter cycle than the horizontal synchronizing signal S0 of the input video signal as a clock signal, and inputs the horizontal synchronizing signal S0 as the clear signal in the previous period to input the period of the horizontal synchronizing signal S0. When continuously counting for a longer period, the count output S2 is output.
The flip-flop 3 is set by this output S2. Second
The counter 4 of (1) counts with the horizontal synchronizing signal S0 as a clock and outputs a count at an arbitrary set count number. However, the counter 4 is reset by the count output S2 of the first counter 2. The flip-flop 3 is reset by this output S4 and outputs the no-signal detection output S3.

The counter 2 outputs the signal S2 after continuous counting for a period longer than the period of the horizontal synchronizing signal S0, that is, when the input signal disappears. The flip-flop 3 is set at S2, and the signalless state starts. On the other hand, since the reset signal S4 is input with a fixed number of input synchronization signals S0 set in the second counter 4 after the set signal S2 and is then counted and output, for example, the n pulse of the signal S0 in FIG. 2B is output. As described above, when there is no continuity or when this is noise, it is not output and S of a preset constant number of pulses is output.
After 0 is input, it is reset and the no signal state is released. In this embodiment, the operation is normal even when the input signal is intermittent or when noise is mixed.

As described above, the case where the horizontal synchronizing signal is input has been described, but the present invention is not limited to this.
A vertical sync signal can also be used. Further, the present invention can detect not only the presence or absence of the video signal but also the deviation of the pulse train from the constant period. Further, although an example in which a flip-flop is used to output no signal is described, the present invention is not limited to this. For example, the internal synchronization signal generation circuit is activated by the counter output indicating the start of no signal, and the input synchronization is performed. You can also use it to stop this at a signal.

[0011]

Since this no-signal detection circuit is composed entirely of digital circuits and detects a no-signal with reference to a pulse from an oscillator that oscillates continuous pulses of a constant period, the detection period varies. Accurate signalless detection with less noise can be performed. Further, since it is a digital circuit, it can be easily integrated into an IC, and it can be integrated into the same chip as other functional parts to save space and reduce cost.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a first embodiment.

FIG. 2A is a schematic block diagram of a second embodiment.
(B) is a timing chart of the main pulse signal of the second embodiment.

[Explanation of symbols]

 1 pulse oscillator 2 counter 3 flip-flop 4 counter S0 horizontal synchronizing signal S2 counter output S3 no signal detection signal

Claims (5)

[Claims] 1. An oscillator that oscillates continuous pulses of a fixed cycle, and a counter that counts the output pulse of the oscillator, clears it with an input pulse train from the outside, and counts and outputs when the cycle of the input pulse train is a fixed value or more A no-signal detection circuit, wherein the output of the counter is a no-signal detection signal of the input pulse train signal. 2. The no-signal detection according to claim 1, wherein a horizontal sync pulse or a vertical sync pulse of the input video signal is used as an input pulse train, and the no-signal of the input video signal is detected to detect the no-signal of the input video signal. circuit. 3. An oscillator that oscillates continuous pulses of a fixed cycle, a counter that counts output pulses of the oscillator, clears it with an input pulse train from the outside, and counts and outputs when the cycle of the input pulse train is a fixed value or more. A no-signal detection circuit comprising a flip-flop that is set by the counter output and reset by the input pulse train, and the output of the flip-flop serves as a no-signal detection signal of the input pulse train signal. 4. An oscillator that oscillates continuous pulses of a fixed period, a first counter that counts the pulses oscillated by the oscillator, clears them with an input pulse train, and outputs a count when the period of the previous pulse train is a fixed value or more. A second counter is provided which counts and outputs when the number of pulses of the input pulse train is a certain number or more and which is cleared by the output of the first counter.
The no-signal detection circuit, wherein the output of the counter is the start of the no-signal of the input pulse train signal, and the output of the second counter is the end of the no-signal. 5. An oscillator that oscillates continuous pulses of a fixed cycle, a first counter that counts the pulses oscillated by the oscillator, clears them with an input pulse train, and outputs a count when the period of the previous pulse train is a fixed value or more. A second counter that counts and outputs when the number of pulses of the input pulse train is a certain number or more and is cleared by the output of the first counter, and a flip-flop that is set by the output of the first counter and reset by the output of the second counter. Signal detection circuit that has the output of the flip-flop as the signalless detection signal of the input pulse train signal.