JPS62257283A - Vertical synchronizing signal detection circuit - Google Patents

Abstract

PURPOSE:To eliminate erroneous operation due to various sounds or noise, etc. and to exactly detect a vertical synchronizing signal with high accuracy by prohibiting the action of an AND circuit for a time approximately equal to the period of a vertical synchronizing signal. CONSTITUTION:A vertical synchronizing separator circuit 1 separates a vertical synchronizing signal (b) of a period V from a composite synchronizing signal (a). A counter circuit 3 counts the oscillating output of a period shorter than the period V of an oscillator 4, and when the counting reaches a prescribed value, transmits a counting output (d) to the AND gate circuit 2 so that an AND output (e) is transmitted to a terminal B as a vertical synchronizing signal. The counter circuit 3 is reset by the AND output of the vertical synchronizing signal C(b) and its own counting output (d), and prohibits the AND output of the AND gate circuit 2 for a period T. In case a composite synchronizing signal (a) including a noise pulse 5 occurred during the duration of a horizontal synchronizing signal is inputted, since an erroneous detection output 6 occurrs within the duration of the prohibiting time T, the output 6 is not outputted from the AND gate circuit 2, hence the vertical synchronizing signal (e) outputed is not influenced by the noise pulse 5.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is used in televisions, etc., and detects vertical synchronization signals to reliably extract only the vertical synchronization signal from a composite synchronization signal in which a vertical synchronization signal is combined with a horizontal synchronization signal, etc. Regarding circuits.

(Prior art) As a conventional vertical synchronization signal detection circuit, Japanese Patent Application No. 51-1
The one shown in No. 29009 is known. In this conventional example, when separating the vertical sync signal from the TV's composite sync signal, the composite sync signal is input to a register that operates with a clock twice the horizontal sync frequency, and the output of that register is used as the vertical sync signal. It is said that Here, the phase relationship among the composite synchronization signal (a), the clock (b), and the separated vertical synchronization signal (e) is shown as shown in FIG.

(Problems to be Solved by the Invention) In the above-mentioned conventional vertical open-light separation circuit, as shown in FIG.
If the noise pulse 5 appears in the ml of two horizontal synchronizations at a position that overlaps with the rising edge of the clock in (b), as in the signal in (a), at that point, the vertical signal as shown in (c) in the same figure appears. There was a problem in that erroneous detection 6 of the synchronization signal occurred.

The present invention has been made in view of the above problems, and is capable of detecting vertical synchronization signals reliably and with high precision without malfunctioning even when sudden noise pulses or noise occur. The purpose is to provide circuits.

(Means for Solving the Problems) In order to solve the above-mentioned problems and achieve the above objects, the vertical synchronization signal detection circuit provided by the present invention detects vertical synchronization signals from composite synchronization signals including vertical synchronization signals with period A vertical synchronization separation circuit that separates a synchronization signal, an excavator that excavates at a period shorter than the period V, a counter circuit that counts the oscillation output of the oscillator, a count output of the counter circuit, and an output of the vertical synchronization separation circuit. The present invention is characterized in that a vertical synchronizing signal is taken out from the output side of the logical product circuit, and the counter circuit is restored by the vertical synchronizing signal.

(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

First, to explain the configuration, 1 is a vertical synchronization separation circuit,
A composite synchronizing signal (a) which is a composite of a vertical synchronizing signal with a period V and a signal is input, the vertical synchronizing signal is separated from this composite synchronizing signal, and only the separated vertical synchronizing signal (b) is output. 4 is an oscillator that oscillates with a period shorter than the period V, and the excavation output of the excavator 4 is sent to the counter circuit 3. The counter circuit 3 counts the oscillation output of the oscillator 40, and the counted value reaches a predetermined value. When it reaches the threshold, it counts up and sends the count output (d) to one input terminal of an AND circuit (hereinafter referred to as an AND gate circuit) 2. The separated vertical synchronization signal (b) from the vertical synchronization separation circuit 1 is input to the other input terminal of the AND gate circuit 2, and the logic of the separated vertical synchronization signal (b) and count output (d) is input. The product output (e) is applied to the reset terminal of the counter circuit 3 to restore the counter circuit 3, and the AND output (e) is sent from the terminal B as a vertical synchronization signal.

Next, the operation of the present invention will be explained in detail using FIG.

When the television composite synchronization signal shown in FIG. 2(a) is input to the vertical synchronization separation circuit l of FIG. 1, a separated vertical synchronization signal as shown in FIG. 2(b) is obtained. Here, FIG. 2(c) is a diagram showing the signal of FIG. 2(b) compressed in the time direction, and V represents the vertical synchronization period. The separated vertical synchronization signal in FIG. 2(c) is combined with the AND in FIG.
It is input to the reset terminal of the counter circuit 3 via the gate circuit 2. The counter circuit 3 is reset by the logical product output of the vertical A light signal shown in FIG. 2(c) and its own counter output shown in FIG. 2(d), and the logical product output of the AND gate circuit 2 is Prohibited during period T in figure (d). After the T period has elapsed, the device enters a state of waiting for the next vertical synchronization signal. AND
The reset signal outputted from the gate circuit 2 to the counter circuit 3 is simultaneously generated.Next, referring to FIG. 3, the operation when there is noise in the composite synchronization signal will be explained.

Figure 3 (a) shows a composite synchronization signal in which a noise pulse 5 occurs between two horizontal synchronization signals due to the influence of noise. Signal (a) with such a waveform is transferred to the vertical synchronization separation circuit of Figure 1. 1, the output of the vertical synchronization separation circuit 1 is an erroneous detection output 6 in a part other than vertical synchronization, as shown in FIG. 3(b).
occurs. Here, FIG. 3(c) is a diagram showing the compressed signal of FIG. 3(b), and V is the vertical synchronization period.

The synchronizing signal in which the erroneous detection of FIG. 3(c) has occurred is inputted to the reset terminal of the counter circuit 3 via the AND gate circuit 2 of FIG. Erroneous detection output 6 is AND gate circuit 2
The output (, ) of the AND gate circuit 2 continues to be at the IL level because it occurs within the range of the prohibition time that prohibits the logical product output.

In other words, the output of the AND gate circuit 2 is stopped as shown in FIG. 3(d), and the erroneous detection output 6 due to noise is
This prevents output from the AND gate circuit 2 in the figure. Therefore, the vertical synchronization axis signal outputted through the output terminal B is the same as the output signal in the case of no noise, as shown in FIG. 2(e), as shown in FIG. Not affected.

In addition, at the time when noise input is prohibited in Fig. 2 (C),
If the stability of the excavation circuit is made high enough, the vertical synchronization period V
It can be brought close to , and the effect of eliminating the influence of noise can be greatly achieved.

Usually, in a television signal encoding device, A/D of the television signal is used.
- A highly stable crystal oscillation circuit is used for D/A conversion and digital processing.

By using the output of this crystal oscillation circuit as the oscillator output of the present invention, the configuration of the present invention can be easily realized by simply adding a counter and an AND gate circuit.

(Effects of the Invention) As described above, according to the present invention, there is provided a vertical synchronization separation circuit that separates a vertical synchronization signal from a composite synchronization signal including a vertical synchronization signal with a period V, and a vertical synchronization signal that oscillates with a period shorter than the period V. An oscillator, a counter circuit that counts the oscillation output of the oscillator, and an AND circuit that inputs the count output of the counter circuit and the output of the vertical synchronization separation circuit are provided, and vertical synchronization is performed from the output side of the AND circuit. At the same time as taking out the signal, the vertical synchronization signal, that is, the AND output, was used to restore the Aki counter circuit. Therefore, the operation of the AND circuit was prohibited for a time approximately equal to the period V, and the noise was detected within this prohibited time. Even if noise or noise occurs, the vertical synchronizing signal can be detected reliably and with high accuracy without causing a word operation.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part of the embodiment of Fig. 1, and Fig. 3 shows the operation of the embodiment of Fig. 1 when a noise pulse occurs. FIG. 4 is a signal waveform diagram of the conventional example, and FIG. 5 is an explanatory diagram showing the operation when a noise pulse occurs in the conventional example. DESCRIPTION OF SYMBOLS 1... Vertical synchronization separation circuit, 2... AND gate circuit, 3... Counter circuit, 4... Issuing JJd%.

Claims (1)

[Claims] a vertical synchronization separation circuit that separates the vertical synchronization signal from a composite synchronization signal including the vertical synchronization signal; an oscillator that oscillates with a cycle shorter than the cycle of the vertical synchronization signal; and a counter circuit that counts the oscillation output of the oscillator; An AND circuit inputting the count output of the counter circuit and the output of the vertical synchronization separation circuit is provided, a vertical synchronization signal is taken out from the output side of the AND circuit, and the counter circuit is reset by the vertical synchronization signal. A vertical synchronization signal detection circuit characterized in that: