JPS63158977A - Field discriminating circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction from being generated and to simplify circuit constitution, by detecting the equalization pulse period of an input composite synchronizing signal in relation to the correlation of a vertical synchronizing pulse, and discriminating an even/odd number field. CONSTITUTION:In an elimination circuit 14, a pulse (c) in which an equalization pulse is eliminated from a composite synchronizing signal (a) is generated, and also, in an extraction circuit 17, a pulse (e) obtained by extracting the vertical synchronizing pulse is generated. The pulse (c) is introduced to detection circuits 20-22, and a pulse (h) outputted only for about 1H after the lapse of 3H of the equalization periods is formed, and in an OR circuit 23, an even number field detecting pulse (i) synchronized with the pulse (e) is formed. Also, the pulse (c) is introduced to a detection circuit 25, and a pulse (j) outputted after the lapse of 4H of the equalization pulse periods which precedes the vertical synchronizing pulse is formed, and in an OR circuit 26, an odd number field detecting pulse (k) synchronized with the pulse (e) is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a field discrimination circuit, and more particularly, to a field discrimination circuit that discriminates between an even field and an odd field of a television signal. .

Conventional technology A conventional field discrimination circuit is disclosed in Japanese Patent Application Laid-Open No. 1986-12.
As described in 8791, there is a first method of determining based on the phase relationship between the edges of the vertical synchronizing signal and the horizontal synchronizing signal, and a second method of determining by counting equalization pulses within the vertical synchronizing signal.

Problems to be Solved by the Invention However, in the first method, the jitter tolerance is small because the differentiating circuit for detecting the edge of the vertical synchronization signal is sensitive to pulse noise and the phase difference is small. Therefore, this method has the problem of causing malfunctions.

Further, the second method has problems in that it is easy to erroneously count pulsed noise, which causes malfunctions, and requires a counter and the like, making the circuit complicated.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a field discrimination circuit that is less likely to malfunction and has a simple circuit configuration.

SUMMARY OF THE INVENTION In the present invention, a cancellation circuit removes the equalization pulse from the incoming composite synchronization signal.

The extraction circuit extracts the vertical sync pulse from the incoming composite sync signal.

The first detection circuit generates and outputs a first detection signal for the invasion 1H when it is detected that the equalization pulse period of the output signal of the removal circuit has passed by 3HI.

The second detection circuit generates and outputs a second detection signal after detecting that the equalization pulse period of the output signal of the removal circuit has elapsed for four days.

The first logic circuit extracts the first detection signal and generates an even field discrimination signal only when a vertical synchronization pulse is supplied from the extraction circuit.

The second logic circuit extracts the second detection signal and generates the odd field discrimination signal only when the vertical synchronization signal is supplied from the extraction circuit.

Operation In the present invention, the equalization pulse of the composite synchronization signal is removed, and it is detected that the equalization pulse period has passed 3H and 4H, respectively. Here, the equalization pulse period preceding the vertical synchronization pulse is 3.58. Taking advantage of the fact that there are 4 days in an odd field, when the detection signal of the equalization pulse period 1113H, which is output for 1H, is obtained during the vertical synchronization pulse period, it is determined that it is an even field, and the equalization pulse The detection signal of 4H between 11 and 11 is vertical IIIJ.
It is determined that the field is an odd number field when the field is obtained in the period pulse period.

Example FIG. 1 shows a circuit configuration diagram of an embodiment of the circuit of the present invention.

In the same figure, the terminal 10 is connected to a composite synchronization signal a as shown in FIGS. 2(A) and 3(A) separated from the television signal.
comes in. FIG. 2(A) shows the start of an even field, and FIG. 3(A>) shows the start of an odd field.

Composite synchronization signal aLt above stable multivibrator (
12 (hereinafter referred to as "mono-multi"), it detects the fall of the composite synchronization signal a and rises, and the pulse width shown in FIG. 2 (B) is larger than the equalization pulse width and smaller than the horizontal synchronization pulse width. , a pulse b shown in FIG. 3(8) is generated. The pulse b is connected to the OR circuit 13 along with the composite direction t11100.
Figure 2 (C) where the equalization pulse is removed.
, a pulse C as shown in FIG. 3(C) is generated. Above L no multi 12. A removal circuit 14 is composed of the A circuit 13.

Further, the composite sync signal a is supplied to the monomulti-15, where it detects the falling edge of the composite sync signal a and rises. ), pulse d shown in FIG. 3(D)
is generated. The pulse d is supplied to the OR circuit 16 together with the composite synchronization signal a, where ! A pulse e as shown in FIG. 2(E) and FIG. 3(E) is generated by extracting the If direct synchronization pulse. Monomulti 15. The OR circuit 16 constitutes an extraction circuit 17.

The output pulse C of the OR circuit 13 is supplied to a retrigger type monomulti 20. The monomulti 20 detects the falling edge of pulse C and falls, and the low level period is greater than 38 (H is the horizontal scanning period) and smaller than 3.5H in Figures 2 (F) and 3 (F). ) is generated. When the pulse C falls during this low level period, the monomulti 20
is retriggered, and the low level period of pulse f is extended.

The monomulti 21 detects the rising edge of the pulse f and generates a pulse Q having a pulse width of approximately 1H as shown in FIGS. 2(G) and 3(G). Pulse " and pulse Q are supplied to the OR circuit 22. The OFF circuit 22 becomes low level during the vertical synchronization pulse period of an even field where the equalization pulse period preceding the vertical synchronization pulse is 3.5H (see FIG. 2). The pulse h shown in Fig. 3 (H) is generated.*In several fields, the pulse h is obtained after the vertical synchronization pulse period ends as shown in Fig. 3 (H).
This is the first detection signal that is output. The monomulti 20 and 21 and the OR circuit 22 constitute a first detection circuit.

This pulse h is supplied together with the pulse e to the OR circuit 23 which is the first logic circuit, where an AND operation of negative logic is performed to detect an even field synchronized with the pulse e as shown in FIG. 2 (1). Pulse i is generated and output from terminal 24. In odd fields, pulse i cannot be obtained as shown in FIG. 3 (!).

Further, the output pulse C of the OR circuit 13 is supplied to a retrigger type monomulti 25 which is a second detection circuit. The monomulti 25 detects the rising edge of pulse C and the pulse width is 4.
A pulse j shown in FIG. 2 (J) and FIG. 3 (J) which is larger than H and smaller than 4.5H is generated. Mono multi 25 outputs mono multi 2 when pulse C rises during the high level output period.
5 is retriggered, and the high level period of pulse j is extended. Pulse jLt! l! ! The equivalent pulse period preceding the direct synchronization pulse becomes a low level during the vertical synchronization pulse period of an odd field of 4H, and becomes a low level after the end of the vertical synchronization pulse period in an odd field. Pulse j is the second detection signal output after the equalization pulse period has elapsed for four days.

This pulse j is supplied to the OR circuit 26, which is a second logic circuit, together with the pulse e, where a negative logic AND operation is performed to detect an odd field synchronized with the pulse e, as shown in FIG. 2(K). Pulse k is generated and output from terminal 27. In an even field, a pulse cannot be obtained as shown in FIG. 3(K).

In this way, it has a simple configuration of monomulti 12.15.20.21゜25 and OR circuit 13.16.22.23.26, and does not have a differentiation circuit or counter, so it is sensitive to pulse noise. jitter tolerance is large, and malfunctions are reduced.

Effects of the Invention As described above, according to the field discrimination circuit of the present invention, there is little risk of sensitivity to pulse noise, high jitter tolerance, low risk of malfunction, and the circuit configuration can be made up to 111 m. It is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of one embodiment of the field discrimination circuit of the present invention, and FIGS. 2 and 3 are timing diagrams for explaining the operation of the circuit shown in FIG. 12.15.20.21.25...Mono multi, 13
．． 16.22.23.26...OR circuit.

Claims (1)

[Claims] A removal circuit that removes equalization pulses from an incoming composite sync signal; an extraction circuit that extracts vertical sync pulses from the incoming composite sync signal; and equalization of the output signal of the removal circuit. A first detection circuit generates and outputs a first detection signal for approximately 1H after detecting that the pulse period has elapsed for 3H, and an equalization pulse period for the output signal of the removal circuit detects that 4H has elapsed. a second detection circuit that generates and outputs a second detection signal; and a first detection circuit that extracts the first detection signal and generates an even field discrimination signal only when a vertical synchronization pulse is supplied from the extraction circuit. and a second logic circuit that extracts the second detection signal and generates an odd field discrimination signal only when a vertical synchronization signal is supplied from the extraction circuit. .