JPH04192884A - Synchronizing signal discriminating circuit - Google Patents

Abstract

PURPOSE:To improve the discrimination accuracy of a synchronizing signal by eliminating the noise of pulse width being shorter than count length of a first counter, and eliminating a noise at the time of receiving a weak electric field. CONSTITUTION:A first counter 1 is made enable in a period in which an input synchronizing signal (b) is in an H level, cleared by an edge signal (c), and thereafter, executes a count operation. Count length of a first counter 1 is shorter than pulse width of the input synchronizing signal (b), therefore, by a normal synchronizing signal, a count output (d) is outputted at the time t2, but when a noise generated at the time t4 is shorter than the count length, the count output (d) is not outputted by an edge signal (c) generated at the time t4. In such a way, the synchronizing signal discriminating circuit which does not cause a malfunction even when a noise, etc., are mixed in can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization signal determination circuit used in a television receiver or the like to determine the input state of a synchronization signal.

(Prior Art) FIG. 4 is a block diagram showing a conventional synchronization signal discrimination circuit. The conventional synchronization signal discriminating circuit shown in the figure includes a counter 2 having a count length longer than the period of the input synchronization signal, and a flip-flop 6.

In FIG. 4, the input synchronization signal is input to the counter 2 and also to the flip-flop 6, clearing the counter 2 and resetting the flip-flop 6. Also,
A count output (RC) g of the counter 2 sets a flip-flop 6, and the counter 2 is configured to operate based on a clock (CLK) a.

5. Regarding the circuit operation of the synchronization signal discriminator circuit shown in Fig. 4.
This will be explained using the timing diagram shown in the figure.

The clock a and the input synchronization signal input to the counter 2 in FIG. 4 are as shown in FIGS. 5(a) and 5(b),
The input synchronization signal is time t. Start up at time to +X
It falls at time T (T is the clock period or an arbitrary positive number) and rises again at time t9, at time t. Assuming that the counter 2 has periodicity such that it falls at +xT, the counter 2 is at time t. The counter 2 is cleared and starts counting at time to +xT, but is cleared again at time t6, which is earlier than the count length, so that the output g of the counter 2 is never output and the flip-flop 6 is not set.

On the other hand, since the input synchronization signal S resets the flip-flop 6, its output (discrimination output) h is as shown in Fig. 5 (C).
It becomes L (low) level as shown in FIG. This discrimination output outputs an L level when the input synchronization signal is properly input.

Furthermore, as shown in FIG. 5(d), if the input synchronization signal exists for a period of time to-t, ) + xT, but there is no input after that, counter 2 will start counting from time t, xT. After starting and counting a predetermined number of times, a count output g is outputted at time t1 as shown in FIG. 5(E).

As a result, the flip-flop 6 is set, and the determination output becomes H (high) level as shown in FIG.

In this way, when the input synchronization signal input to the counter 2 and the flip-flop 6 is inputted normally, the discrimination output outputted by the flip-flop 6 is at L level, and when the input synchronization signal is not inputted, the discrimination output is at L level. becomes H level,
The input state of the input synchronization signal can be determined.

(Problem to be Solved by the Invention) By the way, when the above-described conventional synchronizing signal discriminating circuit is used in a television receiver, etc., under weak electric field reception conditions, as is well known, the conventional synchronizing signal discriminating circuit is provided at the front stage of the synchronizing signal discriminating circuit. A synchronization signal separation circuit (not shown) does not function sufficiently, and noise cannot be avoided. In such a case, in the conventional synchronizing signal discrimination circuit shown in FIG. 4, the counter 2 is cleared by noise even if no synchronizing signal is received, the flip-flop 6 is reset, and the discrimination output becomes L level. However, there is a problem in that the synchronization signal is incorrectly determined to be incoming legitimately.

It is also known that in a synchronization signal separation circuit (not shown), when the amount of mixed noise becomes excessive, the synchronization signal becomes as if it were at H level for the entire period. In this case, the flip-flop 6 in FIG. 4 is always reset and the discrimination output is always at L level, resulting in a malfunction.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a synchronization signal discrimination circuit that does not malfunction even when noise or the like is mixed in.

(Means for Solving the Problems) In order to solve the problems of the conventional technology described above, the present invention has the following features:
a first edge detection means that detects a leading edge of an input synchronization signal and outputs a pulse; and a count operation that is enabled by the input synchronization signal and cleared by the output pulse of the first edge detection means; a first counter that outputs a pulse after counting a predetermined number; and a first counter that is set by the count output of the first counter and reset by the trailing edge of the input synchronization signal, and outputs a pulse in response to the input synchronization signal. a flip-flop, a second edge detection means for detecting the leading edge of the output pulse of the first flip-flop and outputting a pulse, and a count operation that is cleared by the output pulse of the second edge detection means. a 20th counter that outputs a pulse after counting a predetermined number; and a second flip-flop that is set by the count output pulse of the second counter and reset by the output of the second edge detection means to output a discrimination output. The present invention provides a synchronization signal discriminating circuit characterized by comprising:

(Example) Hereinafter, a synchronization signal discrimination circuit of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the synchronous signal discriminating circuit of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the synchronous signal discriminating circuit of the present invention. In addition, in Figure 1, tea 4
Components that are the same as those of the conventional synchronization signal discrimination circuit shown in the figure are given the same reference numerals.

The clock (CLK) a and the input synchronizing signal in FIG. 1 are as shown in FIGS. 2(a) and 2(b).

This input synchronization signal is a regular synchronization signal at time t, a noise at time t4, and a noise at time t.

The odor is at a continuous H level due to excessive noise.

The input synchronization signal is the first counter 1 and the edge detector (
The edge detector 3 detects the leading edge of the input synchronizing signal (see FIG. 2(c)).
As shown in , at time jl+14.1. At this point, an edge signal C, which is a negative pulse, is output.

The first counter 1 is enabled during the H level period of the input synchronizing signal S, and performs a counting operation after being cleared by the edge signal C. Since the count length of the first counter 1 is shorter than the pulse width of the input synchronization signal S, the count output d is output at time t2 with a regular synchronization signal, but the noise occurring at time t4 is shorter than the count length. If so, the count output d is not output depending on the edge signal C generated at time t4.

Then, in a state where the continuous H level starts at time t, the count output d is periodically outputted according to the count length like times t6, t7, etc., and the count output d is shown in FIG. ). This count output d is input to the first flip-flop 5 and sets the first flip-flop 5. Furthermore, since the input synchronization signal is input to the first flip-flop 5 via the inverter 7, the first flip-flop 5 is reset by the trailing edge of the input synchronization signal. Therefore, the output e becomes as shown in FIG. 2 (e).

Furthermore, the output e of the first flip-flop 5 is input to an edge detector (second edge detection means) 4, and the edge detector 4 detects the leading edge of the output e as shown in FIG. The edge signal f is output as follows.

This edge signal f is input to the second counter 2 and the second flip-flop 6, and the second counter 2 and the second flip-flop 6 perform the discriminating operation as explained in the related art. Outputs a discrimination output similar to that shown.

The edge detecting means 3.4 of the first and second cabinets described above is the third
As shown in the figure, a well-known circuit consisting of a flip-flop 8.9 and an AND gate circuit 10 can be used.

(Effects of the Invention) As explained in detail above, according to the synchronization signal discriminating circuit of the present invention, noise with a pulse width shorter than the count length of the first counter is removed, so noise during reception of a weak electric field is eliminated. The second
With this edge detection means, even if the synchronization signal is always at H level, it will not be mistakenly judged as a regular synchronization signal.
This has an extremely excellent practical effect in that the synchronization signal can be determined with high accuracy only when a regular synchronization signal is input.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the synchronous signal discrimination circuit of the present invention, FIG. 2 is a timing diagram for explaining the operation of the synchronous signal discrimination circuit of the present invention, and FIG. 3 is a block diagram showing an embodiment of the synchronous signal discrimination circuit of the present invention. FIG. 4 is a block diagram showing a conventional synchronizing signal discriminating circuit, and FIG. 5 is a timing diagram for explaining the operation of the conventional synchronizing signal discriminating circuit. 1.2...Counter, 3.4...Edge detector (edge detection means), 5.6...Flip-flop. Patent applicant: Victor Japan Co., Ltd. Figure 4

Claims (1)

[Claims] A first device that detects the leading edge of an input synchronization signal and outputs a pulse.
a first counter that is enabled by the input synchronization signal, performs a counting operation by being cleared by the output pulse of the first edge detection means, and outputs a pulse after counting a predetermined number of times; a first flip-flop that is set by the count output of the counter No. 1 and reset by the trailing edge of the input synchronization signal and outputs a pulse in response to the input synchronization signal; a second edge detection means that detects an edge and outputs a pulse; a second counter that is cleared by the output pulse of the second edge detection means, performs a counting operation, and outputs a pulse after counting a predetermined number of times; A synchronous signal discrimination circuit comprising a second flip-flop that is set by a count output pulse of the second counter and reset by an output of the second edge detection means to output a discrimination output.