JPS61248672A - Generating circuit for outside synchronization-typed synchronizing signal with outside synchronizing signal noise gate function - Google Patents

Abstract

PURPOSE:To make it possible to accurately detect a synchronizing signal from an outside synchronizing signal in which a noise is mixed by deciding only an incoming input having a pulse period within a precision set at a pulse period when the outside synchronizing signal supplied from the outside of a system is recognized as a right one, as the right outside synchronizing signal. CONSTITUTION:An outside synchronizing signal 1 supplied from the outside of the system is inputted to an FF4-1 and is sub-sampled by a system clock 3. A counter circuit 6, after it is cleared by the Q-output of an FF4-3, counts the system clock 3. The output of the counter circuit 6 is supplied to comparators 7-1 and 7-2. When the outside synchronizing signal having a wrong pulse period is inputted, the output of an FF5 becomes a low level and a synchronizing pulse generating PLA12 is not initialized and with being controlled in timing as fixed at the previous initialization, a synchronizing signal 2 is outputted and it enables an operation to prevent the defect of the synchronizing signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit for realizing an external synchronization signal noise gate function in a synchronization signal generation circuit that operates in phase synchronization with an external synchronization signal. It is.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional external synchronization type synchronization signal generation circuit. In the figure, 1 is an external synchronization signal supplied from outside the system, 10 is a retrigger type monostable multivibrator (retrigger type MM), 11 is a monostable multivibrator (MM), and 12 is a P L for synchronization signal generation.
A (Programmable Logic Arr.
ay), 2 is a synchronization signal output, and 3 is a system clock.

Next, the operation of the conventional externally synchronized type synchronization signal generation circuit shown in FIG. 3 will be explained. External synchronization signal 1 supplied from outside the system (downward pulse input specification)
is input to the retrigger type monostable multivibrator 10. This retrigger type monostable multivibrator 10 is activated by the falling edge of the external synchronization signal 1 and generates an input mask signal for a predetermined period. The input mask signal is input to the monostable multivibrator 11, which generates a pulse signal with a predetermined pulse width, and is supplied as a reset input to the synchronizing signal generating PLA 12 to initialize the synchronizing signal generating PLA 12.

Therefore, noise mixes into the external synchronization signal 1 supplied from outside the system, and as a result, the input mask signal that is the output of the IJ type monostable multivibrator 0 is connected, and When the pulse signal for resetting is no longer generated, a free-running synchronization signal according to the internal system clock frequency divided by 30 is output, thereby preventing the synchronization signal from being lost.

[Problem that the invention seeks to solve]

In the conventional externally synchronized synchronous signal generation circuit as described above,
It works effectively against noise that enters between 7ξ pulses of external synchronization signal 1 supplied from outside the system, but it works effectively against noise that comes in during the pulse period of external synchronization signal 1, that is, the pulse of external synchronization signal 1 is dropped. If noise exists, the system will be drawn into the noise and malfunction.
Therefore, there is a problem that the synchronization signal output 2 is disturbed by noise.

This invention was made in order to solve this problem, and is an external synchronization type with a stable external synchronization signal noise function that is not affected by noise that comes during the pulse period of the external synchronization signal. The purpose is to obtain a synchronization signal generation circuit.

[Means for solving problems]

The external synchronization type synchronization signal generation circuit with an external synchronization signal noise gate function according to the present invention has an external synchronization signal noise gate function that uses an external synchronization signal with an accuracy set to the pulse period when the external synchronization signal supplied from outside the system is normal. The circuit is configured so that a synchronization signal can be correctly detected from an external synchronization signal mixed with noise by making a determination that only inputs with pulse periods that fall within the range are recognized as correct external synchronization signals.

[Effect]

In the external synchronization type synchronization signal generation circuit with an external synchronization signal noise gate function of the present invention, a counter circuit that operates according to the system clock is operated during the pulse period of the input external synchronization signal, and the count values of the counter circuit are compared. By determining whether or not the synchronization timing is within a predetermined window value, correct synchronization timing can be obtained from an external synchronization signal mixed with noise.

[Laughter side]

FIG. 1 is a block diagram showing an external synchronization type synchronization signal generating circuit with an external synchronization signal noise gate function, which is an embodiment of the present invention. In the figure, 1 is an external synchronization signal supplied from outside the system, 4-1, 4-2, 4-3
is a positive edge-triggered D flip-flop (F/
F-reset), 5 is positive edge trigger type D
7 Ritzo Flotso (with F/F-gate), 6 is a counter circuit, 7-1.7-2 is a comparator that determines the upper and lower limit window values of the pulse period, 8 is A, N D circuit, 9 is N
12 is a PLA for generating a synchronizing signal, 2 is a synchronizing signal output, and 3 is a system clock.

Figure 2 shows the external synchronization signal noise gate function +j in Figure 1.
3 is a timing chart showing signal waveforms of various parts to explain the operation of the externally synchronized type synchronizing signal generating circuit.

Next, the operation of the external synchronization type synchronization signal generating circuit with an external synchronization signal noise gate function, which is an embodiment of the present invention shown in FIG. 1, will be explained with reference to FIG. External synchronization signal 1, which is often supplied from outside the system, is input to F/F 4-1 and sampled by system clock 3 as shown in the Q output of F/F 4-1 shown in FIG. F/F
The Q output of 4-1 is each F/F 4-2, F/F 4
-3, the rising edge of the pulse is detected, and a pulse of one system clock period appears at the outputs of F/F 4-2 and F/F 4-3, respectively. At this time, F/
The Q output of F4-2 can be regarded as the pulse period of external synchronization signal 1. Here, the period during which the output is High is the pulse period. After the counter circuit 6 is cleared by the Q output of the F/F 4-3, it counts the system clock 3 in the above pulse period. The output of the counter circuit 6 is provided to each comparator 7-1, 7-2. Comparator 7-1
A lower limit window value is set for , and when the output of the counter circuit 6 exceeds the lower limit window value, it becomes High.
Provides output. An upper limit window value is set in the comparator 7-2, and when the output of the counter circuit 6 is smaller than the upper limit window value, a High output is supplied. The output of each comparator 7-1, 7-2 is supplied to the input of an AND circuit 8, and the output of this AND circuit 8 is supplied to the F/F 5. F/F5 is switched by the Q output of F/F4-2, so that the output of the AND circuit 8 during the period when the Q output of F/F4-2 outputs Low is the NAND AND circuit 9.
be done. One input of this NANDAND circuit 9 has an F/
The Q output of F4-3 is supplied, and the Q output of this F/F4-3 is
NANDAN at the timing when the output becomes High output
The D circuit 9 is supplied as a clear signal to the synchronization signal generation PLA 12, initializes the synchronization signal generation PLA 12, and controls the timing of the synchronization signal output 2. Here, if external synchronization signal 1 with an incorrect pulse period is input, the output of F/F 5 will be at a LOW level,
The synchronizing signal generating PLA 12 is not initialized, but outputs the synchronizing signal output 2 while being controlled at the timing determined from the previous initialization, and operates to prevent the synchronizing signal from being lost.

In the above embodiment, a case has been described in which a counter circuit 6 for counting the system clock 3 is used, but a monostable multivibrator may be used as long as accuracy and stability are not a concern.

In addition, in the above embodiment, the description is mainly directed to the synchronization signal in the video signal, so the system is implemented using H/W, but the system may be realized by applying a microcomputer to the low-speed synchronization signal. .

〔Effect of the invention〕

As explained above, in an external synchronization type synchronization signal generation circuit with an external synchronization signal noise gate function, the present invention uses a pulse period when the external synchronization signal supplied from outside the system is normal as an external synchronization signal noise gate function. Only pulse inputs that fall within the set accuracy are judged as valid external synchronization signals, making it possible to realize an extremely accurate system configuration, and also to easily convert to Li3. It is effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an external synchronization type synchronization signal generation circuit with an external synchronization signal noise gate function, which is an embodiment of the present invention. FIG. A timing chart showing the signal waveforms of each part to explain the operation of the type synchronization signal generation circuit,
FIG. 3 is a block diagram showing a conventional external synchronization type synchronization signal generation circuit. In the figure, 1... External synchronization signal, 2... Synchronization signal output, 3... System clock, 4-1.4-2゜4
-3.5...Positive edge trigger type Fritsuzo 7
0tsuzo (F/F), 6... counter circuit, 7-1.
7-2...Comparator, 8...AND circuit, 9...N
AND circuit: PLA for synchronizing signal generation. In addition, in each figure, the same code|symbol shows the same or equivalent part=9-. Procedural amendment (spontaneous) 20 Name of invention External synchronous signal generation circuit 3 with external synchronous signal noise gate machine Relation to the person making the amendment Patent applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Representative of Mitsubishi Electric Corporation
- 4. Agent ``Kimoriya Address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, Subject of amendment: Detailed Description of the Invention - I of the specification. 1) Change L I SJ to “L8” on page 9, line 2 of the specification.
Correct it as "I". (2) Figure 1 of the attached drawings is amended as shown in the attached sheet.

Claims (1)

[Claims] In a circuit that generates a system synchronization signal by initializing a synchronization signal generation counter using the noise processing result obtained to extract a synchronization signal from an external synchronization signal mixed with noise, an input signal sequential circuit is used in the noise gate processing section. , an external synchronization signal comprising digital circuits such as a counter circuit, a count value comparison circuit, and a signal determination circuit, and is characterized in that it determines that signals other than those having a pulse period based on a correct synchronization signal waveform are not accepted as input signals. External synchronous type synchronous signal generation circuit with noise gate function.