JPS5951679A - Method and circuit for discriminating composite video signal - Google Patents

Abstract

PURPOSE:To attain the confirmation of input state with less malfunction, by counting a synchronizing pulse is a printer making hard copy of the content of a composite video signal so as to check the normality of the signal and to discriminate the presence of an input. CONSTITUTION:The composite video input signal 1 is inputted to a synchronizing separation circuit 2 and a video signal 5 and a synchronizing signal 6 are outputted. The synchronizing signal 6 is separated into a horizontal synchronizing signal 7 and a vertical synchronizing signal 8 at a horizontal/vertical separating circuit 3. A counter 4 is reset with the signal 8 to count the horizontal synchronizing signal 7. When the level of the synchronizing signal 6 is high with the count number reaching a prescribed value, it is discriminated that the input signal is normal and its discrimination output signal 10 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention takes a composite video signal as input, and converts the content of the signal into
The present invention relates to a composite video signal determination method and its circuit in a hard copy printing device.

Conventionally, when determining the presence or absence of an input signal in this type of device, a method has been used in which a detection circuit is provided and the determination is made based on a negative wave voltage.

In particular, the intermediate frequency signal processing (1F processing) function allows for easy addition of a determination function. However, in a system that receives a composite video signal as input, an independent detection circuit/judgment circuit is required. Furthermore, with these determination methods using a detection circuit, it is difficult to check a noisy signal or the normality of an input signal.

An object of the present invention is to count synchronization pulses, check the normality of an input signal, and at the same time determine the presence or absence of input.

A feature of the present invention is that a synchronization signal is separated from an input composite video signal by a synchronization separation circuit. Furthermore, the synchronization signal is divided into horizontal and vertical synchronization signals by a horizontal/vertical separation circuit. Then, the counter is reset by this vertical synchronization signal, and the number of horizontal synchronization signals is counted. Figure 1 is a block diagram related to the present invention. 1 is a composite video input signal which is input to the synchronization separation circuit 2 and outputs a video signal 5 and a synchronization signal 6. 3 is a horizontal/vertical separation circuit which inputs the synchronizing signal 6 and outputs a horizontal synchronizing signal 7 and a vertical synchronizing signal 8. 4 is a counter, which uses the vertical synchronization signal 8 as a reset input, the horizontal synchronization signal 7 as a count input, and outputs an out signal 14. 9 is a judgment circuit, which receives the out signal 14 and the synchronization signal 6 as input;
The determination output signal 1o is output.

Figure 2 shows the waveforms of each part in Figure 1. Waveform A
, B, and O are waveforms corresponding to the first field; waveform A represents the synchronizing signal 6, waveform B represents the horizontal synchronizing signal 7, and waveform C represents the vertical synchronizing signal 8. In the waveform, F is the synchronization signal 6. corresponding to the second field. Horizontal synchronization signal7. A vertical synchronization signal 8 is shown.

FIG. 3 shows a specific example of the horizontal/vertical synchronization separation circuit 3 shown in FIG. 1, in which a monostable multivibrator 11 receives a synchronization signal 6 as an input and outputs a horizontal synchronization signal 7. The D type flip-flop 12 inputs the horizontal synchronizing signal 7 to the ap terminal, inputs the synchronizing signal 6 to the D terminal, and outputs the vertical synchronizing signal 8 to the Q terminal.

FIG. 4 is a diagram showing the state of interlacing on the television screen 15, where dotted lines 16 indicate the scanning lines of the first field, and real lines #1117 indicate the scanning lines of the second field. One screen is scanned by the dotted line 16 and the solid line 17, and the screen is displayed.

Next, the operation will be explained. Composite video signal 1 is synchronous component 6
The signal is separated into a video signal 5 and a synchronization signal 6 by a circuit 2. Next, this synchronization signal 6 is separated into a horizontal synchronization signal 7 and a vertical synchronization signal 8 by a horizontal/vertical synchronization separation circuit 8. At this time, the horizontal/vertical synchronization separation circuit generates a horizontal synchronization signal with a constant pulse width using a mono multivibrator 11, as shown in FIG. This horizontal pulse is used as a clock pulse for the D type flip-flop 12, and the synchronization signal 6 is used as the D input. At this time, the clock pulse 7 determines its input as the clock of the D flip-flop at the falling edge, and the vertical synchronization signal 8 is outputted.

Next, the counter 4 is reset using this vertical synchronizing signal 8, and the number of horizontal synchronizing signals 7 is counted.

When this count reaches a certain value, for example, NTSO
In the signal, the level of synchronization signal 6 when it reaches 267 is H.
If it is lgH, the input signal is determined to be normal and the result is set to 1.
Output to 0.

The same concept can be achieved even if the device of the counter 41 determination circuit 9 section in FIG. 1 is implemented by a microcomputer (CPU).

According to the present invention, it is possible to control the input situation (f7it) with few malfunctions, and it is also an effective method for determining noise in input signals. , it is practical for a biller featuring a video signal.Furthermore, in the case where it is necessary to determine the odd/even field shown in FIG. 4, the system shown in FIG. With the counter 4 and the determination circuit 9 configured as a CPU, field determination of odd and even numbers is possible by simply changing the prescribed count number of the counter using CPH software.Therefore, the field determination circuit and the input determination circuit are possible with the same hardware configuration.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of the present invention. FIG. 2 shows a timing chart in FIG. 1 of the present invention. FIG. 3 is a more detailed block diagram of FIG. 1 of the present invention. FIG. 4 is an explanation of television interlacing. Applicants: Epson Corporation Representative Patent Attorney Tsutomu Mogami

Claims (1)

[Claims] Using the synchronization signal separated from the composite video signal as an input, the counter is reset by the vertical synchronization signal, and the number of horizontal synchronization signals separated from the synchronization signal is calculated. is counted by the counter, and when a predetermined count is reached, the value of the input synchronization signal is determined, and based on the determination result, the presence or absence of input of the composite video signal is determined. Judgment method and its circuit.