JPH025073B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field frequency discrimination circuit suitable for application to, for example, a monitor receiver of a VTR.

For example, there are VTRs that can record and reproduce television signals of PAL, SECAM, and NTSC systems with a color subcarrier frequency of 4.43 MHz. VTR like this
For monitor receivers used in the It is necessary to switch.

First, a conventional field frequency discrimination circuit will be described with reference to FIG. 1 is an input terminal to which a vertical synchronizing signal separated from the television signal is supplied. This input terminal 1 has
The field frequency is 50 as in PAL and SECAM systems.
field/sec, the number of scanning lines per frame is 625 (hereinafter simply referred to as 50/625 system), or the color subcarrier frequency is 4.43MHz.
A vertical synchronizing signal of a television system (hereinafter simply referred to as 60/525 system) with a field frequency of 60 fields/second and 525 scanning lines per frame, such as the NTSC system, is supplied. The period of these vertical synchronization signals is T ₁ = 16.7 (msec) for the 60/525 system (Figure 2 A), and T ₂ (>T ₁ ) = 20 for the 50/625 system.
(msec) (Figure 2B).

2, 3, and 4 are first, second, and third monostable multivibrators, and the time widths of their respective output pulses are τ ₁ , τ _{2 ,} and τ ₃ (second C, D, and E), respectively.
Then, the relationship between T ₁ , T ₂ ; τ ₁ , τ ₂ , τ ₃ is expressed as τ ₁ <
T ₁ < T ₂ , τ ₁ + τ ₂ ≒ 1/2 (T ₁ + T ₂ ), τ ₁ + τ ₂ + τ ₃
> T ₂ , and τ ₂ is selected to be slightly larger than the time width of the vertical synchronization signal in FIG. 2A, and τ ₃ is selected to be slightly larger than the time width of the vertical synchronization signal in FIG. 2B. Here, τ ₁ =15 (msec), τ ₂ =τ ₃ =3 (msec).

Vibrators 2, 3, and 4 are sequentially connected in cascade,
An input terminal 1 is led out from the input side of a vibrator 2. Then, the vertical synchronization signal from the input terminal 1 and the output pulse of the vibrator 3 (Fig. 2D) are supplied to the first timing comparison circuit 5 for comparison, and the vertical synchronization signal is the signal shown in Fig. 2A. If so, an H (high) comparison pulse is output to the output terminal 6, as shown in Fig. 2B.
If the signal is , an L (low) comparison pulse is output. Also, the vertical synchronization signal from the input terminal 1 and the output pulse of the vibrator 4 (Fig. 2E) are supplied to the second timing comparison circuit 7 for comparison, and it is determined whether the vertical synchronization signal is the signal shown in Fig. 2B or not. output terminal 8
If the comparison pulse of H is the signal of A in Figure 2, then it is L.
comparison pulses are output respectively.

Thus, it is determined whether the received television signal is of the 60/525 format or the 50/625 format based on the comparison pulses of the comparator circuits 5 and 7.

However, the field discriminating circuit shown in FIG. 1 uses a monostable multivibrator having a CR circuit, so it has the disadvantage that it is difficult to integrate it into an IC.

In view of these points, the present invention proposes a field frequency discrimination circuit that is suitable for IC implementation, is resistant to noise, and is difficult to malfunction.

In the first aspect of the present invention, the number of horizontal synchronization signals within one vertical period is M and N, respectively (where M<
N) supplies a vertical synchronization signal and a horizontal synchronization signal for one of the input television signals of the first and second television signals whose field frequencies are Fm and Fn, respectively (where Fm>Fn). By doing this, the field frequency discrimination circuit that determines whether the field frequency of the input television signal is Fm or Fn calculates the number of horizontal synchronization signals from immediately after the arrival of a certain vertical synchronization signal of the input television signal. a first detection for counting and detecting that the arrival point of the next vertical synchronization signal of the input television signal is within a predetermined period before counting S horizontal synchronization signals (where M<S<N); counting the number of horizontal synchronization signals immediately after the arrival of a certain vertical synchronization signal of the input television signal;
The arrival point of the next vertical synchronization signal of the input television signal is S horizontal synchronization signals (where M<S<
N) second detection means for detecting that the field frequency of the input television signal is within a predetermined period after counting, and based on the detection outputs of the first and second detection means, the field frequency of the input television signal is Fm and Fn.

In the second aspect of the present invention, in the first aspect, the output is further cleared by the detection output of the second detection means, and generates an output when a predetermined plurality of detection outputs of the first detection means are counted. and a second counting means that is cleared by the detection output of the first detection means and generates an output when a predetermined number of detection outputs of the second detection means are counted. Based on the outputs of the first and second counting means, it is determined whether the field frequency of the input television signal is Fm or Fn.

An embodiment in which the present invention is applied to a field frequency discrimination circuit for discriminating the field frequency of the above-mentioned 60/525 format and 50/625 format television signals will be described below with reference to FIG.

Now, the number of horizontal synchronization signals within one vertical period is 262.5 in the 60/525 system, and 50/62
In the case of 5 methods, the number is 312.5. Also, the horizontal frequencies are approximately equal in both methods. Therefore, the number approximately halfway between the two is set as a reference value, for example 288, and the number of horizontal synchronization signals within one vertical period is counted using a counter, and the number of horizontal synchronization signals is determined to reach the reference value or within a predetermined range less than the reference value. If it is detected whether the frequency is within the range, it is possible to determine the field frequency of the television signal of the above-mentioned two systems. The field frequency discrimination circuit shown in FIG. 3 is based on this idea.

In FIG. 3, FF1, FF2, . 11 and 12 are 50/625 and 60/5 respectively
This is an input terminal to which a horizontal synchronizing signal HD (FIG. 4) and a vertical synchronizing signal VD (FIG. 4) of the X.25 system are supplied.

13 is cleared by the vertical synchronization signal VD (Fig. 4), and the horizontal synchronization signal HD (Fig. 4) is cleared by 288
Outputs a pulse (Figure 4) when counting.
The 290-decimal counter circuit is composed of a 64-decimal counter 14, an octal counter 15, and an AND circuit 16.

In the embodiment shown in FIG. 3, the 290-decimal counter circuit 13 counts the number of horizontal synchronization signals of the input television signal immediately after the arrival of the vertical synchronization signal, and The arrival point of the next vertical synchronization signal is S (=288) horizontal synchronization signals [however, M (=262.5)]
<S (=288) <N (312.5)] This corresponds to the second detection means that detects that it is after counting.

The 64-decimal counter 14 is a counter that is cleared by the vertical synchronizing signal VD and outputs a pulse (FIG. 4) when 32 horizontal synchronizing signals HD are counted, and is composed of flip-flop circuits FF1 to FF6. The octal counter 15 is a counter that is cleared by the vertical synchronizing signal VD and outputs a pulse (Fig. 4) when four pulses have been counted.
It is composed of flip-flop circuits FF7 to FF9. In this case, the counters 14 and 15 constitute a 512-base counter circuit 17. Therefore, this counter circuit 17 is cleared by the vertical synchronizing signal VD and outputs a pulse when it counts 256 horizontal synchronizing signals HD. Then, the pulses and are supplied to the AND circuit 16, and an output signal is output. This pulse output signal is obtained from the 50/625 horizontal synchronization signal.
HD and vertical synchronization signal VD are input terminal 11, respectively.
12. This pulse is 288 (=256
It rises when +32) horizontal synchronizing signals HD are counted, and falls when the vertical synchronizing signal VD arrives.
Therefore, based on the pulse output from the AND circuit 16, it is determined that the received television signal is of the 50/625 format.

18 is a gate signal generating circuit, from which a gate signal (FIG. 4) and a vertical synchronizing signal VD are supplied to an AND circuit 19.

In the embodiment shown in FIG. 3, the circuit consisting of the gate signal generation circuit 18 and the AND circuit 19 calculates the number of horizontal synchronization signals of the input television signal immediately after the arrival of a certain vertical synchronization signal, according to the gist of the present invention. The arrival time of the next vertical synchronization signal of the input television signal is the horizontal synchronization signal S (=
288) [However, M (262.5) < S (= 288) < N
(312.5)] The first step to detect before counting
This falls under the detection means of

This gate signal generation circuit 18 includes a counter circuit 13, an inverter circuit 20, AND circuits 21, 32
It is composed of a forward counter 22 and an inverter circuit 23. That is, the output is supplied to the inverter circuit 20 and inverted, the output 〓 (FIG. 4) and the pulse are supplied to the AND circuit 21, and the output pulse D (FIG. 4) is sent to the 32-decimal counter 22 as a clear pulse. Supplied. This pulse rises at the 256th horizontal synchronization signal HD, falls at the 288th horizontal synchronization signal HD in the 50/625 system, and
In the case of the 5th system, this is a pulse that falls when the vertical synchronizing signal VD arrives.

The counter 22 outputs a pulse when counting 16 horizontal synchronizing signals HD, and is composed of flip-flop circuits FF10 to FF14. The output pulse of the counter 22 is supplied to the inverter circuit 23 and inverted, and the output pulse (FIG. 4) is supplied to the AND circuit 19 as a gate signal.

As shown in FIG. 4, the output of this counter 22 normally changes to "0" and "1" alternately every time it counts 16 horizontal synchronizing signals HD, but it is cleared by a pulse. When this occurs, counting of the horizontal synchronization signal HD is stopped during the period from the rise to the fall of that pulse.

Therefore, in the case of the 60/525 system, as shown in FIG.
It rises when 256 HDs are counted and falls when 275.5 HDs are counted, so this is connected to AND circuit 1.
9, the 60/525 vertical synchronization signal VD
can be gated like a pulse.

In addition, in the case of the 50/625 system, the pulse rises when 256 horizontal sync signals HD are counted after the arrival of the vertical sync signal VD, and falls when 304 are counted, so this pulse is supplied to the AND circuit 19. too,
The 50/625 vertical synchronization signal VD is not gated.

Thus, only if the vertical synchronization signal VD supplied to the input terminal 12 is of the 60/525 format,
The output F (FIG. 4) of the AND circuit 19 becomes the vertical synchronizing signal VD, and it is determined that the received television signal is of the 60/525 format.

By the way, if noise is mixed in with the pulse, there is a possibility that the 50/625 and 60/525 formats will be incorrectly determined. Therefore, counters 24 and 25 of a predetermined number, for example, both hexadecimal, are provided, and the pulse is supplied to the input terminal of the counter 24 and the clear terminal of the counter 25, and the pulse is supplied to the input terminal and the clear terminal of the counter 25, respectively. 4, 5) and F
(Fig. 4, Fig. 5), only one of them is plural,
Here, when eight consecutive pulses occur, pulse H (FIG. 5) or pulse G (FIG. 5) is outputted to the output side of each pulse. The counter 24 is composed of flip-flop circuits FF19 to FF22, and the counter 25 is composed of flip-flop circuits FF15 to FF.
Consists of 18.

In the embodiment of FIG. 3, the counters 25, 24
is cleared by the detection output of the second detection means in the second gist of the present invention, and the first
a first counting means that generates an output when a predetermined number of detection outputs of the detection means are counted; and a second counting means that is cleared by the detection output of the first detection means;
The second counting means generates an output when a predetermined plurality of detection outputs of the detection means are counted.

And pulses H and G are inverter circuit 2
RS flip-flop circuit 28 through 6, 27
are supplied to the set and reset terminals, respectively.
The non-inverting output terminal and the inverting output terminal of the flip-flop circuit 28 are output terminals 29 and 30, respectively.
is derived. Thus, when a 50/625 format television signal is received, the output of the output terminal 29 becomes H, and when a 60/525 format television signal is received, the output of the output terminal 30 becomes H.

Next, another embodiment of the present invention will be described with reference to FIG. 6. Parts corresponding to those in FIG.

Now, the number of horizontal synchronization signals within one vertical period is, as mentioned above, in the 60/525 system.
262.5 pieces, and 312.5 pieces for the 50/625 method.
Therefore, we set the number approximately in the middle between the two as a reference value, for example,
288, a predetermined width above and below the reference value, for example, a lower limit value of 48, which is 240, and an upper limit value, which is 336. Then, use a counter to count the number of horizontal synchronizing signals within one vertical period, and if the number is between the lower limit and the upper limit, whether it is between the lower limit or the reference value or between the reference value and the upper limit. If it is detected, the field frequencies of the two types of television signals mentioned above can be determined. The field discrimination circuit shown in FIG. 6 is based on this idea.

In FIG. 6, FF1, FF2, ..., FF24 are flip-flop circuits constituting a counter to be described later, but the flip-flop circuit FF in FIG.
1, FF2, ..., FF22.
These flip-flop circuits FF1, FF2,...
Each output of the FF 24 is shown with the same number in FIGS. 7, 8, and 9. Also, the pulses or outputs in FIGS. 6 to 9 are also similar to those in FIGS. 3 to 5.
It is separate from the pulse or output shown in the figure.

31 is cleared by a pulse (described later) related to the vertical synchronization signal VD (Figs. 7 and 8), and is also cleared by the horizontal synchronization signal HD (Fig. 7).
It is a 242-decimal counter circuit that outputs a pulse (Fig. 7, Fig. 8) when counting 240 pieces (Fig. 7, Fig. 8).
It is composed of a 64-base counter 32, a 4-base counter 33, and an AND circuit 34. The 64-decimal counter 32 is cleared by the pulse and the horizontal synchronization signal
This counter outputs a pulse when 32 HDs are counted, and is composed of flip-flop circuits FF1 to FF6. The 4-ary counter 33 is a counter that is cleared by a pulse and outputs a pulse when it counts two outputs from the flip-flop circuit FF6 of the 64-ary counter 31.
Consists of FF7 and FF8. Then, each output pulse of the flip-flop circuits FF5, FF6, FF7 and FF8 is supplied to the AND circuit 34, and the AND circuit 34 outputs a pulse B.

A circuit 35 generates pulses related to the vertical synchronizing signal VD, and is composed of a NAND circuit 36 and an RS flip-flop circuit 37. The horizontal synchronizing signal HD and the pulse are supplied to the NAND circuit 36, and the output pulse is supplied to the flip-flop circuit 37.
A vertical synchronizing signal VD is supplied to the reset input terminal of the circuit, and a pulse is output from its inverted output terminal. As shown in FIGS. 7 and 8, this pulse rises when 241 horizontal synchronizing signals HD are counted after the arrival of a certain vertical synchronizing signal VD, and falls when the next vertical synchronizing signal VD arrives. Since the counter circuit 32 is cleared by this pulse, there is no risk of erroneous clearing due to noise, compared to clearing by the vertical synchronizing signal VD itself.
Furthermore, even if the vertical synchronization signal VD is lost midway, a clearing operation is performed.

Reference numeral 38 denotes a noise removal circuit for removing noise in the vertical synchronization signal, which is composed of an inverter circuit 39, an AND circuit 40, and a ternary counter 41. Vertical synchronization signal VD is supplied to AND circuit 40 through inverter circuit 39. Also, a horizontal synchronizing signal HD and a flip-flop circuit 46 to be described later.
The pulse from the inverted output terminal of is supplied to the ternary counter, and the output of the counter 41 is sent to the AND circuit 40.
is supplied to The vertical synchronizing signal from this AND circuit from which noise has been removed is supplied to AND circuits 49 and 50, which will be described later.

The ternary counter 41 is a flip-flop circuit.
FF9, FF10, OR circuit 42 and AND circuit 4
Consists of 3. Then, the horizontal synchronizing signal HD is supplied to the flip-flop circuit FF9, and its output is supplied to the flip-flop circuit FF10 and the AND circuit 43.
An output of 0 is supplied to the AND circuit 43. Then, the output of the AND circuit 43 and the pulse E from the flip-flop circuit 46 (described later) are sent to the OR circuit 43.
and its output is a flip-flop circuit.
It is supplied to FF9 and FF10 as a clear pulse.

49 and 50 are AND circuits to which a vertical synchronizing signal from the noise removal circuit 38 is supplied, and gate signals from a gate signal generation circuit 51 (FIGS. 7 and 8), which will be described later. , Figure 8),
(Figures 7 and 8), gated at 50/625 and 6, respectively.
Discrimination pulses (FIG. 7) and (FIG. 8) corresponding to the 0/525 vertical synchronization signal are output.

51 is a gate signal generation circuit, which includes a 242 advance counter circuit 31, a ternary counter 41, inverter circuits 44, 45, and RS flip-flop circuits 46, 64.
It consists of a forward counter 47 and an inverter circuit 48.

In the embodiment of FIG. 6, a circuit comprising an AND circuit 50 and a gate signal generation circuit 51 counts the number of horizontal synchronization signals of an input television signal immediately after the arrival of a certain vertical synchronization signal, according to the gist of the present invention. Then, the arrival time of the next vertical synchronization signal of the input television signal is S(=288) above the horizontal synchronization signal.
[However, M (= 262.5) < S (= 288) < N (312.5)
]
This corresponds to the first detection means for detecting that it is before counting.

Further, in the embodiment shown in FIG. 6, the circuit consisting of the AND circuit 49 and the gate signal generation circuit 51 calculates the number of horizontal synchronization signals of the input television signal immediately after the arrival of the vertical synchronization signal, according to the gist of the present invention. The arrival time of the next vertical synchronization signal of the input television signal is equal to the horizontal synchronization signal S (=288).
[However, M (= 262.5) < S (= 288) < N (312.5)
]
This corresponds to the second detection means that detects that the count has been completed.

The pulse from the 242 binary counter circuit 31 is sent to the flip-flop circuit 4 via the inverter circuit 44.
6 set input terminals. The output of the flip-flop circuit FF10 of the ternary counter 41 is 64
It is supplied to the advance counter 47. The counter 47 is composed of flip-flop circuits F11 to F16, and when it counts 32 outputs from the ternary counter 41, it outputs a pulse (Figs. 7 and 8) and 16
When counting, a pulse (Figures 7 and 8) is output. The pulse is then supplied through the inverter circuit 45 to the reset input terminal of the flip-flop circuit 46. The flip-flop circuit 46 operates at the falling edge of the input signal, and outputs pulses from the non-inverting and inverting output terminals, respectively (Figs. 7 and 8).
) is output. The pulse rises at the 240th horizontal synchronization signal HD as shown in Figures 7 and 8.
This is the pulse that falls at the 336th (=240+96)th pulse, and
The pulse is a pulse with the opposite phase of the pulse. The pulses are supplied to a ternary counter 41 and 64
It is supplied to the advance counter 47 as a clear pulse.

The pulse from the 64-ary counter 47 is a pulse that rises at the 288th horizontal synchronization signal and falls at the 336th as shown in FIGS. 7 and 8, and the pulse from the inverter circuit 48 is a pulse whose phase is It is reversed. Then, by supplying the pulse F to the AND circuit 49 as a gate signal, when the television signal being received is of the 50/625 format, the pulse F is supplied to the AND circuit 49 as shown in FIG.
9 and is supplied to the input terminal of the hexadecimal counter 24 and the clear terminal of the hexadecimal counter 25. Also, the AND circuit 50 receives a pulse and a pulse
is supplied as a gate signal ×〓 (Figs. 7 and 8), so that when the received television signal is of the 60/525 format, a pulse is output from the AND circuit 50 as shown in Fig. 8. It is supplied to the input terminal of the hexadecimal counter 25 and the clear terminal of the hexadecimal counter 24. Note that the counter 24 is composed of flip-flop circuits FF21 to FF24, and the counter 25 is composed of flip-flop circuits FF17 to FF2.
Consists of 0.

In the embodiment of FIG. 6, like the embodiment of FIG. 3, the counters 25 and 24 are cleared by the detection output of the second detection means according to the second gist of the present invention, and A first counting means that generates an output when a predetermined number of detection outputs of the first detection means are counted, and a detection output of the second detection means, which is cleared by the detection output of the first detection means; and a second counting means that generates an output when a predetermined plurality of numbers are counted. Then, pulse (Fig. 7, Fig. 9) and pulse (Fig. 8, Fig. 9)
When only one of (Fig.) is 8 consecutive,
A pulse is sent to the counter 24 or 25, respectively (Fig. 7,
9) or pulses (FIGS. 8 and 9) are output and supplied to the set and reset input terminals of the flip-flop circuit 28 through inverter circuits 26 and 27, respectively. The non-inverting output terminal and the inverting output terminal of the flip-flop circuit 28 are led out to output terminals 29 and 30, respectively. Thus, when receiving a 50/625 format television signal, the output of the output terminal 29 becomes "H", and when receiving a 60/525 format television signal, the output of the output terminal 30 becomes "H".

According to the present invention described above, it is possible to obtain a field frequency discrimination circuit that is suitable for IC implementation, is resistant to noise, and is difficult to malfunction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional field discrimination circuit, FIG. 2 is a waveform diagram, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIGS. 4 and 5 are the same as in FIG. Waveform diagrams for the embodiment, FIG. 6 are block diagrams showing other embodiments of the present invention, FIGS. 7 and 8.
9 and 9 are waveform diagrams for the embodiment of FIG. 6. 13 and 31 are counter circuits as first counter means, 24 and 25 are counters as second and third counter means, respectively, and 28 is a flip-flop circuit.

Claims (1)

[Claims] 1. The number of horizontal synchronization signals within one vertical period is
Input television of either one of the first and second television signals, which are M and N (M<N), respectively, and whose field frequencies are Fm and Fn (Fm>Fn), respectively. By supplying a vertical sync signal and a horizontal sync signal of the signal, the field frequency of the input television signal is adjusted to the
In the field frequency discrimination circuit that determines whether the input television signal is Fm or Fn, the number of horizontal synchronization signals is counted immediately after the arrival of the vertical synchronization signal with the input television signal, and the number of horizontal synchronization signals is counted immediately after the input television signal is input. a first detection means for detecting that the synchronization signal arrives within a predetermined period before counting S horizontal synchronization signals (where M<S<N); Immediately after the arrival of the vertical synchronization signal, the number of horizontal synchronization signals is counted, and the arrival time of the next vertical synchronization signal of the input television signal is determined by counting the number of horizontal synchronization signals (M<S<N). and a second detection means for detecting that the field frequency of the input television signal is within a predetermined period after the Fm. and Fn. 2 The number of horizontal synchronization signals within one vertical period is
Input television of either one of the first and second television signals, which are M and N (M<N), respectively, and whose field frequencies are Fm and Fn (Fm>Fn), respectively. By supplying a vertical sync signal and a horizontal sync signal of the signal, the field frequency of the input television signal is adjusted to the
In the field frequency discrimination circuit that determines whether the input television signal is Fm or Fn, the number of horizontal synchronization signals is counted immediately after the arrival of the vertical synchronization signal with the input television signal, and the number of horizontal synchronization signals is counted immediately after the input television signal is input. a first detection means for detecting that the synchronization signal arrives within a predetermined period before counting S horizontal synchronization signals (where M<S<N); Immediately after the arrival of the vertical synchronization signal, the number of horizontal synchronization signals is counted, and the arrival time of the next vertical synchronization signal of the input television signal is determined by counting the number of horizontal synchronization signals (M<S<N). a second detection means for detecting that a predetermined period has elapsed after the second detection means; and the second detection means is cleared by the detection output of the second detection means, and a predetermined number of detection outputs of the first detection means are counted. a first counting means that generates an output when the first counting means is cleared by the detection output of the first detection means, and generates an output when a predetermined plurality of detection outputs of the second detection means are counted; and a second counting means, which determines whether the field frequency of the input television signal is Fm or Fn based on the outputs of the first and second counting means. Field frequency discrimination circuit.