JP2002344239A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit, which can supply a stable clock signal to an internal circuit by mask-processing only unstable clock signal, immediately after an oscillation has started in the integrated circuit, having an oscillation circuit which has an oscillation stop means. SOLUTION: The semiconductor integrated circuit comprises the oscillation circuit, which can be oscillated by connecting an oscillation element having an inductance and a capacitor and which supplies clock signal as an oscillation output to the internal circuit. The integrated circuit further comprises the oscillation stoppage means having a NAND circuit 1, and a mask-processing circuit 7, which mask-processes only the clock signal, immediately after a state is made to change from the stoppage of the oscillation to the start of the oscillation, so as not to transmit the signal to the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an LC oscillation in an oscillation circuit built in the semiconductor integrated circuit.

[0002]

2. Description of the Related Art In the prior art, in a circuit for counting an oscillation clock, the count from the start of oscillation has been unstable.

FIG. 8 shows a configuration of an oscillation circuit built in a conventional semiconductor integrated circuit, and FIG. 9 shows an operation timing. 1 is a two-input NAND circuit, and 2 is one input terminal of the NAND circuit 1, which is an external terminal of the semiconductor integrated circuit. 3
The oscillation stop signal is input to the other input terminal of the NAND circuit. Reference numeral 4 denotes an output terminal of the NAND circuit, which is connected to an external terminal of the semiconductor integrated circuit. Reference numeral 5 denotes an inverter circuit to which the output of the output terminal 4 is input, and 8 denotes an output terminal of the inverter circuit 5 for supplying a clock to an internal circuit. 9 is an external inductance for oscillation (hereinafter, L
) Is connected to an external terminal of the semiconductor integrated circuit composed of the input terminal 2 and the output terminal 4. 10 and 1
1 is an external capacitor for oscillation (hereinafter referred to as C),
Each is connected between an external terminal of the semiconductor integrated circuit constituted by the input terminal 2 and the output terminal 4 and the GND potential.

Conventionally, as shown in FIG. 8, the oscillation starts in synchronization with the rise of the oscillation stop signal supplied to the input 3 of the NAND circuit 1, and the inverter circuit 5
The clock is supplied to the internal circuit from the output 8 of.

However, when the oscillation stop signal supplied to the input 3 of the NAND circuit 1 is in a stopped state, that is, in a low potential state, the input 2 of the NAND circuit 1 and the output 4 of the NAND circuit 1 are each in a high potential state. From this state, when the oscillation stop signal supplied to the input 3 of the NAND circuit 1 changes to the oscillating state, that is, the high potential state, the potentials of the input 2 of the NAND circuit 1 and the output 4 of the NAND circuit 1 simultaneously decrease, and When the potential of the input 2 of the NAND circuit 1 falls below the threshold value of the NAND circuit 1, the potential of the output 4 of the NAND circuit 1 starts to rise, and thereafter, the potential of the input 2 of the NAND circuit 1 and the potential of the output 4 of the NAND circuit 1 become , N
Oscillation starts while the potential of the AND circuit 1 is inverted with respect to the threshold value.

Here, the threshold value of the inverter circuit 5 is adjusted to the threshold value of the NAND circuit 1 in order to transmit a clock to the internal circuit even when the oscillation amplitude becomes small. For this reason, the case where the inverter circuit 5 reacts and the case where it does not react are unstable.

[0007] With such a problem, when counting the clock from the start of oscillation to measure the time, the count is shifted by one count. For example, in an on-screen display (hereinafter referred to as OSD) function, when an oscillation is started in synchronization with the rising edge of HSYNC and a clock is counted and displayed at an arbitrary position, if the count becomes unstable, the display on the display becomes unstable. The display position becomes unstable, jitter occurs in the OSD display, and the display quality deteriorates.

[0008]

SUMMARY OF THE INVENTION According to the present invention, there is provided a semiconductor integrated circuit provided with an oscillation circuit having an oscillation stopping means for solving only the unstable clock signal immediately after the start of oscillation. It is an object of the present invention to obtain a semiconductor integrated circuit capable of supplying a stable clock signal to an internal circuit by performing a mask process.

[0009]

The semiconductor integrated circuit according to the first aspect of the present invention can oscillate by connecting an oscillating element including an inductance and a capacitor, and supplies a clock signal as an oscillation output to an internal circuit. Stop means for stopping oscillation in a semiconductor integrated circuit having a built-in oscillator circuit for masking only the clock signal immediately after the state is changed from oscillation stop to oscillation start and not transmitting it to the internal circuit Means.

The semiconductor integrated circuit according to the second aspect of the present invention can oscillate by connecting an oscillating element consisting of an inductance and a capacitor, and incorporates an oscillating circuit for supplying a clock signal as an oscillating output to an internal circuit. A semiconductor integrated circuit having oscillation stop means for stopping oscillation, receiving a clock signal from the oscillation element by first and second inverters having different threshold values, and immediately starting oscillation from an output of the first inverter. And an extraction processing circuit for extracting only the first clock signal of the above, and using the clock signal output from the extraction processing circuit as a mask signal, masking the output of the second inverter and supplying the masked signal to an internal circuit, thereby stopping oscillation. Masks only the first clock signal immediately after changing the state from oscillation to start of oscillation and does not transmit it to the internal circuit And it has a disk processor.

In the semiconductor integrated circuit according to a third aspect of the present invention, in the first or second aspect, the oscillation stop means receives an oscillation stop signal at one input terminal and a clock signal from the oscillation element at another input terminal. , And the output of the NAND circuit is supplied to the mask processing means.

According to a fourth aspect, in the first to third aspects, a clock signal supplied from the oscillation element to the mask processing means is received from an input side of the oscillation stop means.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, a clock signal from an oscillation element input to the other input terminal of the NAND circuit is supplied to the mask processing means. It is.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing an overall configuration according to the first embodiment. FIG. 2 is a waveform chart showing operation timing. FIG. 3 is a connection diagram showing a configuration of the mask processing circuit according to the first embodiment. FIG. 4 is a connection diagram showing a detailed configuration of the mask processing circuit according to the first embodiment. FIG. 5 is a waveform chart showing operation timings of the mask processing circuit according to the first embodiment.

FIG. 1 shows the configuration of the first embodiment according to the present invention, and FIG. 2 shows the operation timing. In the figure,
1 is a two-input NAND circuit, and 2 is one input terminal of the NAND circuit 1, which is an external terminal of the semiconductor integrated circuit. Reference numeral 3 denotes another input terminal of the NAND circuit 1 to which an oscillation stop signal is input. An output terminal 4 of the NAND circuit 1 is connected to an external terminal of the semiconductor integrated circuit.
5 is an inverter circuit which receives the output 4 of the NAND circuit 1 as an input and has a threshold value equivalent to that of the NAND circuit 1, 7 is a mask circuit for masking the first clock immediately after the start of oscillation, 8
Is an output terminal of the mask circuit for supplying a clock to the internal counter. Reference numeral 9 denotes an external inductance for oscillation (hereinafter referred to as L), which is an input 2 of the NAND circuit 1 and NAN.
The output 4 of the D circuit 1 is connected to an external terminal of the semiconductor integrated circuit. Reference numerals 10 and 11 denote oscillating external capacitors (hereinafter referred to as C) connected between the external terminal of the semiconductor integrated circuit at the input 2 of the NAND circuit 1 and the output 4 of the NAND circuit 1, respectively, and the GND potential.

Before the oscillation clock signal is supplied to the internal circuit as shown in FIG. 1, the clock signal immediately after the start of unstable oscillation is masked, so that a stable clock can be supplied to the internal circuit.

FIGS. 3 and 4 show the configuration of the mask processing circuit 7 for masking the first clock signal immediately after the start of oscillation in the first embodiment, and FIG. 5 shows the operation timing.
In the figure, 3 is an input terminal to which an oscillation stop signal is input,
5 is an inverter circuit having a threshold value equivalent to that of the NAND circuit 1, 6 is an inverter circuit having a threshold value higher than that of the NAND circuit 1 and the inverter circuit 5, 13 is an output of the inverter circuit 6, and 14 is an inverter. A signal obtained by inverting the output 13 of the circuit 6 with an inverter, and 12 is a mask circuit for masking the output of the inverter circuit 6 and the oscillation stop signal 3 except for the first clock of the output 13 of the inverter circuit 6 immediately after the start of oscillation. The extraction circuit 15 extracts only the first clock signal of the output 13 of the inverter circuit 6 immediately after the start of oscillation. Reference numeral 15 denotes the output of the extraction circuit 12.

In the first embodiment, since the configuration shown in FIG. 3 is employed, the output 15 of the extraction processing circuit 12 except for the first clock immediately after the start of oscillation of the inverter circuit 6 having a high threshold value is output. By ANDing the output of the inverter circuit 5 having a threshold value equivalent to that of the NAND circuit 1, only an unstable clock signal immediately after the start of oscillation of the inverter circuit 5 can be masked.

FIG. 4 shows an embodiment of the extraction processing circuit 12.
As shown in the figure, the oscillation stop signal 3 goes into a low potential state, the output of the inverter circuit 6 is enabled every time oscillation stops, and then the oscillation stop signal 3 goes into a high potential state. When the output of the inverter circuit 6 outputs a clock once when the signal is released, the clock after that is output until the oscillation stop signal 3 becomes the low potential state.
Disable the output of

According to the present invention, it is possible to realize a circuit for masking the first unstable clock immediately after the start of oscillation, to prevent the unstable clock immediately after the start of oscillation from being supplied to the internal circuit, and to suppress the clock from the start of the oscillation. Even when time is measured by counting, stable counting can be realized.

According to the first embodiment of the present invention, it is possible to oscillate by connecting an oscillating element consisting of an inductance 9 and capacitors 10 and 11, and to supply a clock signal as an oscillation output to an internal circuit. In a semiconductor integrated circuit having a built-in oscillation circuit, oscillation stop means for stopping oscillation is provided, and first and second inverters 5 and 6 having different thresholds receive a clock signal from the oscillation element. An extraction processing circuit 12 for extracting only the first clock signal immediately after the start of oscillation from the output of the inverter 6 is provided, and the clock signal output from the extraction processing circuit 12 is used as a mask signal to mask the output of the second inverter 5. And supply it to the internal circuit,
A mask processing circuit comprising a mask processing circuit for masking only the first clock signal immediately after the state is changed from oscillation stop to oscillation start and not transmitting the clock signal to an internal circuit; A NAND circuit 1 receiving an oscillation stop signal 3 at its other input terminal and receiving a clock signal from the oscillation element at its other input terminal.
Since the output of the ND circuit 1 is supplied to the mask processing means comprising the mask processing circuit 7, in the semiconductor integrated circuit having the oscillation circuit having the oscillation stop means, only the unstable clock signal immediately after the start of the oscillation is output. By performing the mask processing, a semiconductor integrated circuit which can supply a stable clock signal to the internal circuit can be obtained.

Embodiment 2 FIG. Second Embodiment A second embodiment according to the present invention will be described with reference to FIGS. FIG. 6 is a connection diagram showing a configuration according to the second embodiment. FIG. 7 is a waveform chart showing timing in the second embodiment. In the second embodiment, the configuration other than the specific configuration described here has the same configuration as the first embodiment described above, and has the same operation. In the drawings, the same or corresponding parts have the same reference characters allotted.

The circuit according to the second embodiment of the present invention
FIG. 6 shows the case where the input circuit 2 is connected to the input 2 of the AND circuit 1, and FIG. 7 shows the timing. Oscillator NAN immediately after oscillation starts
Since the waveform of the output 4 of the D circuit 1 is inverted when the potential of the input 2 exceeds the threshold value of the NAND circuit 1, the inverted potential is different depending on variations in device characteristics, L and C values, and the like. If the output of the oscillation clock is connected to the output 4 of the NAND circuit 1, the inverter circuit 6
It is considered that the inversion occurs near the threshold value of.

In order to solve such a problem, the extraction of the clock is connected to the input 2 of the NAND circuit 1. By connecting the extraction of the clock to the input 2 of the NAND circuit 1, the inverted potential is surely lowered to the threshold value of the NAND circuit 1, so that the clock immediately after the start of oscillation reliably reaches the threshold value of the inverter circuit 6. .

According to the present invention, the clock immediately after the start of oscillation reliably changes to the threshold value of the NAND circuit 1, and the NAND circuit 1 and the inverter circuit 5 for generating a clock for the unstable clock extraction processing circuit 12 are generated. The clock of the inverter circuit 6 having a threshold higher than the threshold can be generated stably.

According to the second embodiment of the present invention, it is possible to oscillate by connecting an oscillating element consisting of an inductance 9 and capacitors 10 and 11, and to supply a clock signal as an oscillation output to an internal circuit. In a semiconductor integrated circuit having a built-in oscillation circuit, oscillation stop means for stopping oscillation is provided, and first and second inverters 5 and 6 having different thresholds receive a clock signal from the oscillation element. An extraction processing circuit 12 for extracting only the first clock signal immediately after the start of oscillation from the output of the inverter 6 is provided. The output of the second inverter 5 is masked using the clock signal output from the extraction processing circuit 12 as a mask signal. Supply to the internal circuit, only the first clock signal immediately after the state changes from oscillation stop to oscillation start A mask processing means comprising a mask processing circuit 7 which performs a clock processing and does not transmit the clock to an internal circuit. The oscillation stopping means receives an oscillation stop signal at one input terminal 3 and a clock from the oscillation element at the other input terminal 2. A NAND circuit 1 for receiving a signal;
By supplying the clock signal from the oscillation element input to the other input terminal 2 of the ND circuit 1 to the mask processing means comprising the mask processing circuit 7, the clock signal supplied from the oscillation element to the mask processing means is changed. Since the oscillation stop means is received from the input side, in a semiconductor integrated circuit having an oscillation circuit having the oscillation stop means, the clock signal supplied to the mask processing means is stabilized,
It is possible to obtain a semiconductor integrated circuit capable of more accurately masking only an unstable clock signal immediately after the start of oscillation and supplying a stable clock signal to an internal circuit.

[0027]

According to the first aspect of the invention, oscillation can be achieved by connecting an oscillation element including an inductance and a capacitor, and an oscillation circuit for supplying a clock signal as an oscillation output to an internal circuit is built in. In a semiconductor integrated circuit, an oscillation stopping means for stopping oscillation is provided,
Since there is mask processing means for masking only the clock signal immediately after changing the state from oscillation stop to oscillation start and not transmitting the clock signal to the internal circuit, the semiconductor integrated circuit provided with the oscillation circuit having the oscillation stop means has a function to start oscillation. It is possible to obtain a semiconductor integrated circuit capable of supplying a stable clock signal to an internal circuit by masking only the immediately unstable clock signal.

According to the second aspect of the present invention, the semiconductor integrated circuit can oscillate by connecting an oscillating element consisting of an inductance and a capacitor, and incorporates an oscillating circuit for supplying a clock signal as an oscillating output to an internal circuit. The circuit includes an oscillation stopping means for stopping the oscillation, wherein the first and second inverters having different thresholds receive the clock signal from the oscillation element, and receive the clock signal from the output of the first inverter immediately after the start of the oscillation. The clock signal output from the extraction processing circuit is used as a mask signal, and the output of the second inverter is masked and supplied to an internal circuit, so that the clock signal is output from the extraction processing circuit to the internal circuit. Mask processing means that masks only the first clock signal immediately after changing the state to the start and does not transmit it to the internal circuit Therefore, in a semiconductor integrated circuit provided with an oscillation circuit having an oscillation stop means, an unstable state immediately after the start of oscillation can be obtained by a mask processing means having an extraction processing circuit provided with first and second inverters having different threshold values. A semiconductor integrated circuit capable of supplying a stable clock signal to an internal circuit by masking only the clock signal can be obtained.

According to a third aspect of the present invention, in the first or second aspect, the oscillation stop means receives the oscillation stop signal at one input terminal and receives the clock signal from the oscillation element at the other input terminal. Circuit, and the N
Since the output of the AND circuit is supplied to the mask processing means, in the semiconductor integrated circuit having the oscillation circuit having the oscillation stop means, only the unstable clock signal immediately after the start of the oscillation is mask-processed, and the output is stabilized. A semiconductor integrated circuit that can supply a clock signal to an internal circuit can be obtained.

According to the fourth invention, in the first to third inventions, a clock signal supplied from the oscillation element to the mask processing means is received from the input side of the oscillation stop means. In a semiconductor integrated circuit having an oscillating circuit having means, a clock signal supplied to a mask processing means is stabilized, and only an unstable clock signal immediately after the start of oscillation is masked more accurately, and a stable clock signal is generated. A semiconductor integrated circuit that can be supplied to an internal circuit can be obtained.

According to the fifth aspect, in the third aspect, the clock signal from the oscillating element input to the other input terminal of the NAND circuit is supplied to the mask processing means. In a semiconductor integrated circuit having an oscillation circuit having means, the clock signal supplied to the mask processing means is further stabilized, and only the unstable clock signal immediately after the start of oscillation is more accurately masked,
A semiconductor integrated circuit that can supply a stable clock signal to an internal circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing an overall configuration according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing operation timing according to the first embodiment of the present invention.

FIG. 3 is a connection diagram showing a configuration of a mask processing circuit according to the first embodiment of the present invention.

FIG. 4 is a connection diagram showing a detailed configuration of a mask processing circuit according to the first embodiment of the present invention.

FIG. 5 is a waveform chart showing operation timings of the mask processing circuit according to the first embodiment of the present invention.

FIG. 6 is a connection diagram showing an entire configuration according to a second embodiment of the present invention.

FIG. 7 is a waveform chart showing operation timing according to the second embodiment of the present invention.

FIG. 8 is a connection diagram showing a configuration in a conventional technique.

FIG. 9 is a waveform chart showing operation timing in the related art.

[Explanation of symbols]

1 2 input NAND circuit, 2, 3 input terminal of NAND circuit 1, 4 output terminal of NAND circuit 1, 5, 6 inverter circuit, 7 mask processing circuit, 8 output terminal of mask processing circuit 7, 9 external connection for oscillation Inductance, 1
0,11 External capacitor for oscillation, 12 Extraction processing circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B079 BA16 BB05 5J043 AA12 AA25 BB01 DD07 DD12 5J081 AA03 CC31 CC33 DD04 DD15 EE02 EE03 FF03 FF07 FF18 GG04 GG06 KK04 LL05 MM01

Claims (5)

[Claims] An oscillator can be oscillated by connecting an oscillating element including an inductance and a capacitor, and stops oscillation in a semiconductor integrated circuit having an oscillating circuit for supplying a clock signal as an oscillation output to an internal circuit. A semiconductor integrated circuit, comprising: an oscillation stopping means for causing a mask processing means for masking only a clock signal immediately after changing a state from oscillation stop to oscillation start and not transmitting the clock signal to an internal circuit. 2. Oscillation can be achieved by connecting an oscillation element consisting of an inductance and a capacitor, and the oscillation is stopped in a semiconductor integrated circuit having an oscillation circuit for supplying a clock signal as an oscillation output to an internal circuit. An oscillation stopping means for causing the first and second inverters having different thresholds to receive the clock signal from the oscillation element, and extracting only the first clock signal immediately after the start of oscillation from the output of the first inverter A processing circuit having a clock signal output from the extraction processing circuit as a mask signal, masking the output of the second inverter and supplying the masked signal to an internal circuit, thereby changing the state from oscillation stop to oscillation start. Mask processing means for masking only the first clock signal immediately after and not transmitting it to an internal circuit. Semiconductor integrated circuit. 3. The oscillation stopping means is constituted by a NAND circuit receiving an oscillation stop signal at one input terminal and receiving a clock signal from the oscillation element at another input terminal, and outputting the output of the NAND circuit to the mask processing means. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is supplied to the semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 1, wherein a clock signal supplied from said oscillation element to said mask processing means is received from an input side of said oscillation stop means. 5. The semiconductor integrated circuit according to claim 3, wherein a clock signal from an oscillation element input to the other input terminal of said NAND circuit is supplied to said mask processing means.