JP2002073201A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a microprocessor which is capable of quickly switching a low speed mode to a high speed mode, and facilitating countermeasures to an unexpected situation even at the time of switching the mode. SOLUTION: In this microprocessor incorporating a PLL circuit for forming an oscillation pulse with relatively high frequencies obtained by multiplying a clock pulse with relatively low frequencies as a reference frequency input, in a low speed mode, the operation of the PLL circuit is stopped, and a system clock signal corresponding to the relatively low frequencies is outputted, and in a high speed mode, the PLL circuit is started according to the generation of an event whose high speed processing is necessary, and then the system clock signal corresponding to the relatively low frequencies is continuously outputted until the PLL circuit is stabilized, and a request for the start of the high speed processing is issued, and a system clock signal corresponding to the oscillation pulse with the relatively high frequencies formed by the PLL circuit is outputted when the output frequencies of the PLL circuit are stabilized, and the request for the start of the high speed processing is issued.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, which is used, for example, in a portable information terminal having an input pen and has a function of multiplying the frequency of a system clock using a PLL (phase locked loop) circuit. The present invention relates to a technique that is particularly effective when used in a microcomputer of a chip.

[0002]

2. Description of the Related Art A so-called portable information terminal or PDA (PDA) having an input pen for a man-machine interface and a microprocessor of a stored program type.
personal Digital Assistan
t). In such a portable information terminal, the average power consumption of the microprocessor is reduced by selectively setting the operation mode of the microprocessor to a low-speed or high-speed mode in accordance with the processing content. A method for reducing power consumption is adopted.

That is, when the portable information terminal is in a state of displaying characters or the like or in a state of waiting for writing to end, ie, in a standby state, the microprocessor executes relatively simple processing, and the processing load is light. Therefore, the frequency of the clock signal for the microprocessor can be made relatively low and the microprocessor can be operated in the low-speed mode, so that the power consumption of the microprocessor, that is, the portable information terminal, is correspondingly reduced. However, when the writing of characters and the like with the input pen is completed and its recognition becomes necessary, the microprocessor does not need to execute relatively complicated processing such as pattern identification of the written characters and retrieval of matching characters by a dictionary in a short time. The processing burden increases rapidly. For this reason,
It is necessary to increase the frequency of the clock signal for the microprocessor and operate it in high-speed mode.
Accordingly, the power consumption of the microprocessor increases, and the power consumption of the portable information terminal also increases. As described above, by selectively setting the operation mode of the microprocessor to the low-speed or high-speed mode in accordance with the processing content, the average power consumption of the microprocessor is reduced, and the power consumption of the portable information terminal is reduced. A method is adopted.

On the other hand, there is known a PLL circuit which generates an output clock signal which is phase-synchronized with an input clock signal and has a frequency which is a predetermined number of times, and there is a microprocessor incorporating such a PLL circuit. Prior to the present invention, the present inventors have considered using a microprocessor having a built-in PLL circuit in a portable information terminal or the like. In this case, power consumption is achieved by using an input clock signal of the PLL circuit as a system clock signal of the microprocessor in a standby state, that is, a low-speed mode, and using an output clock signal of the PLL circuit as a system clock signal of the microprocessor in a high-speed mode. Can be switched.

As a microprocessor having a built-in PLL circuit, for example, S sold by Hitachi, Ltd.
There is an H2 / 7600 series microprocessor.

Incidentally, in a microprocessor having a built-in PLL circuit, when it is considered that an input clock signal and an output clock signal of the PLL circuit are selectively used as a system clock signal of the microprocessor, the operation flow of the microprocessor is, for example, as follows. As shown in FIG. When the microprocessor is set to the low-speed mode (step ST11), the operation of the PLL circuit is stopped, and a clock signal having a relatively low frequency is supplied as a system clock signal to each part of the microprocessor including the central processing unit CPU. Is done. Thereby, the microprocessor is operated at a relatively low speed, and its power consumption is reduced.

When a high-speed request is recognized in step ST13, the PLL circuit is activated at that time. Whether or not the frequency of the output clock signal from the activated PLL circuit is stabilized is checked in step ST15. Until it is confirmed that the frequency of the output clock signal is stable, the system clock signal to the microprocessor is stopped in step ST14 to prevent the clock pulse having an unstable frequency from being supplied to the microprocessor. it can. Step ST
When the operation of the PLL circuit is confirmed to be stable at 15, a high-speed clock signal which is an output clock signal of the PLL circuit is supplied to the microprocessor as a system clock signal. Thereby, the central processing unit CPU and the like shift to the high-speed mode (step ST16), and the high-speed processing required for character recognition and the like is started. When the end of the processing such as character recognition is recognized in step ST17, the microprocessor is set to the low-speed mode (step ST17).
11).

[0008]

The present inventor has noticed that the configuration considered prior to the present invention has the following problems. That is, it is necessary to take a relatively long time from when a request for starting high-speed processing is made to when the system clock signal is switched to the high-speed clock. This is because a relatively long time is required until the operation of the PLL circuit, that is, the frequency of the output signal is stabilized. During this period, the supply of the system clock signal to the microprocessor is stopped, so that the operation of each unit of the microprocessor including the central processing unit CPU is stopped. As a result, if an unexpected event such as a priority process or a failure occurs during the supply stop period of the system clock signal, it cannot be dealt with, and the reliability of the microprocessor decreases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprocessor having a function of switching from a low-speed mode to a high-speed mode at a high speed and having a function of coping with an unexpected situation even at the time of mode switching.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a PL that forms a relatively high frequency oscillation pulse by multiplying a relatively low frequency clock pulse as an input clock signal of a reference frequency and multiplying the same by a reference frequency
In a microprocessor having a built-in L circuit, in a low-speed mode, the operation of the PLL circuit is stopped, and a clock pulse of a relatively low frequency is supplied to the microprocessor as a system clock signal. In response to the generation, the PLL circuit is started, and the relatively low-frequency clock pulse is continuously supplied to the microprocessor as a system clock signal until the PLL circuit is stabilized and a high-speed processing start is requested. When the output frequency of the PLL circuit is stabilized and there is a request to start high-speed processing, a relatively high-frequency oscillation pulse generated by the PLL circuit is supplied to the microprocessor as a system clock signal.

[0012]

According to the above means, the microprocessor can be quickly switched from the low-speed mode to the high-speed mode when a request for starting the high-speed processing is made. Also, P
Since the clock signal corresponding to the low-speed mode is continuously supplied to the microprocessor as a system clock signal even after the LL circuit is activated until the output frequency is stabilized, the microprocessor operates continuously. It is possible to deal with an unexpected situation such as occurrence of a priority process or a failure. As a result, it is possible to realize a microprocessor that switches from the low-speed mode to the high-speed mode at a high speed and has a function that can cope with an unexpected situation even when the mode is switched.

[0013]

FIG. 1 is a block diagram showing an embodiment of a clock pulse generating circuit CPG incorporated in a microprocessor according to the present invention. Each block in the figure is
According to a known semiconductor integrated circuit manufacturing technique, it is formed on one semiconductor substrate such as single crystal silicon together with other blocks constituting a microprocessor.

In FIG. 1, XTAL, EXTAL, C
KEXT and CKRATE are external terminals provided in the microprocessor. Among these external terminals, a crystal oscillator having a predetermined natural frequency is connected to the external terminals XTAL and EXTAL. , An oscillation pulse having a relatively low frequency corresponding to the low-speed operation mode is formed. Note that the oscillation circuit XOSC is selectively activated by receiving the high level of the control signal CKEXT supplied to the control terminal on. This control signal CKEXT is also used as a control signal of the multiplexer MUX1 described below. As a result, the oscillation circuit XOSC according to the control signal CKEXT
While selectively stopping the operation of the external terminal EXTAL.
Can be supplied from

The multiplexer MUX1 is controlled by the control signal CKEXT. That is, the multiplexer MUX1 switches between using the oscillation pulse from the built-in oscillation circuit XOSC or using the clock pulse supplied from the external terminal EXTAL according to the level of the control signal CKEXT. External terminal EXTA
When the clock pulse from L is used, the control signal C
The operation of the oscillation circuit XOSC is stopped by KEXT. Therefore, the external terminals XTXL and EXTAL
It is not necessary to connect a crystal oscillator.

A relatively low first frequency clock pulse ckr (second clock signal) output from the multiplexer MUX1 is supplied to the input terminal of the 1/2 frequency divider DIV1 and serves as a clock generator. PLL
The signal is supplied to a reference frequency input terminal REF of the circuit (PLL), and further supplied to one input terminal of a multiplexer MUX4 serving as an output selection switching circuit.

The 分 divider circuit DIV1 divides the frequency of the second clock signal, that is, the clock pulse ckr, to form a clock pulse ck1 (fourth clock signal) having a half frequency. The clock pulse ck1 is
The signal is supplied to the other input terminal of the multiplexer MUX4, and is also supplied to one input terminal of a multiplexer MUX3 serving as a switching circuit for output selection.

The PLL circuit has a reference frequency input terminal REF
Input clock signal, ie, clock pulse c, supplied to
kr based on the clock pulse DV1 having a second frequency, that is, an integer multiple thereof.
(Third clock signal). This clock pulse DV1 is supplied to the other input terminal of the multiplexer MUX3 and to the input terminal of the frequency divider DIV2. In this embodiment, the frequency dividing circuit DIV2
Are two divided outputs d2 and d corresponding to the high-speed mode.
4 is formed. These divided outputs are provided by a multiplexer M
Oscillation input terminal OS of the PLL circuit selectively through UX2
C.

The multiplexer MUX2 has an external terminal CK.
One of the two types of frequency-divided outputs d2 and d4 is selected by the switching control signal CKRATE supplied to RATE and transmitted to the oscillation input terminal OSC of the PLL circuit. For example, when the divided output d2 is selected, the PLL circuit works to match the phase of the divided output d2 with the phase of the reference frequency input REF. Therefore, the output of the PLL circuit, that is, the clock pulse DV1 has a frequency multiplied by the reciprocal of the frequency division ratio. Similarly, when the divided output d4 is selected, the PLL circuit outputs the divided output d4.
4 and the reference frequency input REF are operated so as to have the same phase, and the output clock pulse DV1 has a frequency multiplied by the reciprocal of the frequency division ratio. From these facts, the PLL circuit is used for high-speed mode.
The clock pulse DV1 having different frequencies can be selectively formed.

In this embodiment, the PLL circuit comprises:
The operation is selectively stopped in accordance with the start signal supplied to the control terminal PLLON, that is, the output signal of the OR (OR) gate OG1. One and other input terminals of the OR gate OG1 are connected to a PLL control signal P from a clock controller CKC (to be described later with reference to FIGS. 8 and 11).
An LLON and a PLL standby signal PLLSB are supplied, respectively. Note that PLL control signals PLLON and P
The LL standby signal PLLSB is selectively set to a high level by setting a predetermined control register by a central processing unit to be described later, and is used for controlling the activation of the PLL circuit. Therefore, for example, when a microprocessor is used in a portable information terminal, the PLL standby signal is set to a high level when writing of characters by the input pen is started, that is, when the occurrence of an event requiring high-speed processing is recognized. , The PLL circuit is activated in advance to stabilize its output frequency, and it becomes possible to prepare for the start of high-speed processing.

The PLL circuit has a control terminal PLLO
N, that is, when the output of the OR gate OG1 is set to the high level, that is, the PLL control signal PLL
When either the ON state or the PLL standby signal PLLSB is set to the high level, it is selectively activated to perform the above-described multiplication control of the clock signal. In other words, the operation of the PLL circuit is controlled by the PLL control signal PLLON.
And both the PLL standby signal PLLSB and the PLL standby signal PLLSB are set to the low level, thereby selectively stopping the operation. As a result, in the low-speed mode, the operation of the PLL circuit is stopped, and unnecessary current consumption is suppressed. Electricity can be achieved.

The multiplexer MUX3 has a clock enable signal CKEN from the clock controller CKC.
And the selection control signal COSEL1 is supplied to the multiplexer MUX4, and the selection control signal COSEL2 is supplied to the multiplexer MUX4. Among them, the clock enable signal CKEN is
Normally, the level is set to the high level, and is temporarily set to the low level when the microprocessor is switched from the low-speed mode to the high-speed mode. The selection control signal COSEL1 is at a low level when the microprocessor is in the low-speed mode, and is at a high level when the microprocessor is in the high-speed mode.
The selection control signal COSEL2 is selectively set to a high level when it is desired to switch the frequency of a system clock signal cks described later for some reason.

When the clock enable signal CKEN is set to the high level and the selection control signal COSEL1 is set to the low level, the multiplexer MUX3 sets the frequency dividing circuit DUX.
Select clock pulse ck1 output from IV1,
It is supplied as a first system clock signal CK1 (first clock signal) to a first internal circuit including the central processing unit CPU. Also, the clock enable signal CKEN
Is high and the selection control signal COSEL1 is high, the clock pulse DV1 output from the PLL circuit is selected and supplied to the central processing unit CPU and the like as the system clock signal CK1. When the clock enable signal CKEN is set to low level, the output of the multiplexer MUX3 is fixed at low level. As a result, the selection control signal COSEL1
Can be selectively set to the low level or the high level, the microprocessor MPU can be selectively set to the low speed mode or the high speed mode, and when switching from the low speed mode to the high speed mode, the clock enable signal CKEN is temporarily set. By setting the system clock signal CK1 to the low level and temporarily suspending the operation, the operation of the central processing unit CPU or the like at the time of mode switching can be stabilized.

On the other hand, when the selection control signal COSEL2 is at a low level, the multiplexer MUX4 selects the clock pulse ck1 output from the frequency dividing circuit DIV1 and uses it as a system clock signal cks (second system clock signal). The signal is supplied to a second internal circuit including the BSC. Also, the selection control signal COSEL2
Is high, the clock pulse ckr output from the multiplexer MUX1 is selected and supplied to the bus controller BSC and the like as the system clock signal cks. During a normal operation, the selection control signal COSEL2 is at a low level, and the system clock signal cks is at the lowest frequency according to the output of the frequency divider DIV1, that is, the clock pulse ck1.

As described above, the output of the PLL circuit, that is, the clock pulse DV1 has a frequency that is an integral multiple of the output of the multiplexer MUX1, that is, the clock pulse ckr.
The output of the frequency dividing circuit DIV1, that is, the clock pulse ck1
Is the half frequency. Therefore, the first internal circuit including the central processing unit CPU operates in accordance with the clock pulse ck1 having the lowest frequency in the low-speed mode, so that the power consumption thereof is relatively small. DV1
, The power consumption thereof is made relatively large. Needless to say, in the high-speed mode, since the frequency of the system clock signal CK1 is high, the central processing unit C
The processing capability of the PU or the like is enhanced, and the microprocessor can perform high-speed processing suitable for character recognition in a portable information terminal, for example.

FIG. 2 is a block diagram showing one embodiment of the PLL circuit included in the clock pulse generation circuit CPG of FIG. In the figure, a reference frequency input REF and an oscillation input OSC are supplied to a phase comparator, and the up / up and down signals corresponding to the phase difference (frequency difference) between the reference frequency input REF and the oscillation input OSC by the phase comparator. / DOWN (here, for a so-called inverted signal or the like which is selectively set to a low level when it is made valid, a / is added to the beginning of the name; the same applies hereinafter). The control signal up signal / UP and down signal / DOWN formed by the phase comparator are:
It is supplied to a low-pass filter (loop filter) including a charge pump circuit, and is converted into a control voltage VCNT. The control voltage VCNT is supplied to a voltage-controlled oscillator to control its frequency. The output signals P1 and P2 of the voltage controlled oscillator become the clock pulse DV1 after being frequency-divided by a 1/2 frequency divider. The operation of the low-pass filter and the voltage-controlled oscillator is controlled by the control terminal PL.
The operation is selectively stopped in accordance with the control signal supplied to the LON, whereby the operation of the PLL circuit is selectively stopped.

FIG. 3A is a circuit diagram of one embodiment of the voltage controlled oscillator included in the PLL circuit of FIG. In the figure, a control voltage VCNT is supplied to the gate of an N-channel MOSFET Q30 whose source is grounded. This MOSFET Q30 has a control voltage V
The CNT is converted into a current corresponding to the potential, and so-called voltage / current conversion is performed. Such an N-channel type MOSFE
The current signal formed by the TQ30 is passed through a current mirror circuit composed of P-channel MOSFETs Q31 and Q32, and the P-channel MOSFET and the N-channel MOSFET constituting the inverter circuit of the ring oscillator. P-channel MOSFET for current control connected in series
And to a diode-coupled N-channel MOSFET Q34. Among the MOSFETs forming the inverter circuit, the N-channel MOSFET includes a current-controlling N-channel MOSFET configured to form a current mirror circuit with the diode-coupled N-channel MOSFET Q34.
FETs are connected in series.

As a result, a current corresponding to the potential of the control voltage VCNT flows through each inverter circuit constituting the ring oscillator as its operating current. Therefore, when the potential of the control voltage VCNT increases, the operating current of the inverter circuit increases, the signal propagation delay time of the inverter circuit forming the ring oscillator decreases, and the oscillation frequency of the voltage-controlled oscillator increases. Conversely, when the potential of the control voltage VCNT decreases, the operating current of the inverter circuit decreases, the signal propagation delay time of each inverter circuit forming the ring oscillator increases, and the oscillation frequency of the voltage controlled oscillator decreases. Become.

In this embodiment, the gate circuits G30 and G31 are inserted into a cascaded inverter circuit constituting a ring oscillator of a voltage controlled oscillator, and the gate circuits G3 and G3 are driven in accordance with a control signal from a control terminal PLLON.
The gates of 0 and G31 are selectively closed so that the oscillation operation can be selectively stopped. When oscillation stops,
In a voltage controlled oscillator, an N-channel MOSFET Q3
3 is turned on, and the control voltage VCNT is
Since the circuit is forcibly set to the ground potential via the ETQ 33, the operating current via the current mirror circuit is cut off.

FIG. 3B is a circuit diagram of one embodiment of the 1/2 frequency divider included in the PLL circuit of FIG. In the same figure, the 1/2 frequency dividing circuit corresponds to FIG.
And a master-slave flip-flop circuit in which the output signal of the voltage-controlled oscillator or its inverted signal is received as a trigger signal, and the output signal of the slave latch is fed back to the input of the master latch. The master latch and the slave latch divide the output signal P1 by half, and generate clock pulse signals DV2 and DV1.
To form Note that P of the clock pulse generation circuit CPG is
The output signals of the LL circuit and the frequency divider DIV1 are actually two-phase clock pulses D each having a predetermined phase relationship.
V1 and DV2 and ck1 and ck2,
In this specification, the description will be mainly focused on the clock pulses DV1 and ck1.

FIG. 4A is a circuit diagram of one embodiment of the phase comparator included in the PLL circuit of FIG. In the figure, a phase comparator identifies a phase difference between a reference frequency input REF and an oscillation input OSC, and selectively forms an up signal / UP and a down signal / DOWN having a pulse width corresponding to the difference. That is, when the frequency of the oscillation input OSC is lower than the reference frequency input REF, the up signal / UP of the pulse width corresponding to the frequency difference (phase difference)
To form Conversely, when the frequency of the oscillation input OSC is higher than the reference frequency input REF, a down signal / DOWN having a pulse width corresponding to the frequency difference (phase difference) is formed.

FIG. 4B is a circuit diagram showing one embodiment of the charge pump and the low-pass filter of the PLL circuit shown in FIG. In the figure, a P-channel type MOSF
The ETQ 41 is selectively turned on in response to the high level of the control signal from the control terminal PLLON, whereby the low-pass filter is selectively turned on. An up signal / UP is supplied to another P-channel MOSFET Q42 connected in series to the P-channel MOSFET Q41 through two inverter circuits connected in series. The capacitor C has the above 2
The charge-up current flows through the P-channel MOSFETs Q41 and Q42 and the resistors R1 and R2. A discharge current further flows through the capacitor C through the resistors R1 and R2 and the N-channel MOSFET Q43. A down signal / DOWN is inverted by an inverter circuit at the gate of the N-channel MOSFET Q43. Supplied.

As a result, the capacitor C is charged up only during the period when the up signal / UP is at the low level, so that the reference frequency input REF and the oscillation input O
The potential of the control voltage VCNT is increased according to the phase difference of SC. On the other hand, the capacitor C has a down signal / DOW.
Since the discharge is performed only during the period when N is at the low level, the potential of the control voltage VCNT is lowered according to the phase difference between the reference frequency input REF and the oscillation input OSC. Note that an external capacitor (not shown) for lowering the cutoff frequency of the low-pass filter can be connected to the terminal CEXT.

FIG. 5A is a circuit diagram of one embodiment of the multiplexer MUX3 included in the clock pulse generation circuit CPG of FIG. In the figure, a multiplexer MUX3 includes AND gates AG3 and AG4 which receive an output signal of a PLL circuit, that is, a clock pulse DV1 or a divided output of a frequency dividing circuit DIV1, that is, a clock pulse ck1, at one input terminal thereof. Among these, the other input terminal of the AND gate AG3 has a clock enable signal C
The output signal of the AND gate AG2 receiving the KEN and the selection control signal COSEL1 is supplied to the AND gate AG4.
Clock input signal CKE
An output signal of the AND gate AG1 receiving N and the inverted signal of the selection control signal COSEL1 by the inverter V1 is supplied. The output signal of the AND gate AG3 is supplied to one input terminal of the OR gate OG2,
The output signal of G4 is supplied to the other input terminal of the OR gate OG2.

Thus, the multiplexer MUX3 has:
The clock enable signal CKEN is set to a high level,
When the selection control signal COSEL1 is at a low level, the frequency-divided output of the frequency divider DIV1, that is, the clock pulse ck1 having a relatively low frequency is selected to be the system clock signal CK1, the clock enable signal CKEN is at a high level, and When the selection control signal COSEL1 is set to the high level, the output of the PLL circuit, that is, the clock pulse DV1 having a relatively high frequency is selected and used as the system clock signal CK1. As a result, the processing speed of the microprocessor is selectively switched to the low speed or high speed mode.

FIG. 5B is a circuit diagram of an embodiment of the multiplexer MUX4 included in the clock pulse generation circuit CPG of FIG. Note that the multiplexer M
UX1 and MUX2 have the same circuit configuration.

In FIG. 5B, the multiplexer MU
X4 has a multiplexer MUX1 at one input terminal.
Output, ie, clock pulse ckr or frequency dividing circuit D
AND gates AG5 and AG6 receiving the output of IV1, ie, clock pulse ck1, and an OR gate OG3 receiving the output signals of AND gates AG5 and AG6 at a pair of input terminals thereof, respectively. AND gate A
The other input terminal of G5 has a selection control signal COSEL2
And the other input terminal of the AND gate AG6 is supplied with an inverted signal from the inverter V2.

Thus, the multiplexer MUX4 has:
When the selection control signal COSEL2 is set to a high level,
The clock pulse ckr output from the multiplexer MUX1 is selected and used as the system clock signal cks.
When the selection control signal COSEL2 is at a low level, the clock pulse ck1 output from the frequency divider DIV1 is selected and used as the system clock signal cks. As described above, the selection control signal COSEL2 is normally at a low level, and the system clock signal cks is formed according to the clock pulse ck1 having the lowest frequency.

FIG. 6 is a signal waveform diagram of one embodiment of the clock pulse generating circuit CPG of FIG. In the figure, a clock pulse ckr supplied to a reference frequency input terminal REF of the PLL circuit is a pulse signal of a relatively low frequency corresponding to the natural frequency of the crystal resonator coupled to the external terminals XTAL and EXTAL, Dividing circuit DV
The frequency-divided output of one, that is, the clock pulse ck1, is a pulse signal having a half frequency. As described above, the PLL circuit controls the PLL operation control signal PLLON or PLL
When any one of the standby signals PLLSB is set to the high level, the operation is selectively activated, and the clock pulse c
A clock pulse DV1 having an integral multiple of kr, that is, for example, twice the frequency is generated. This clock pulse DV
1 is frequency-divided by, for example, half by a frequency dividing circuit DIV2 to become a frequency-divided output d2, which is supplied to an oscillation input terminal OSC of the PLL circuit.

As a result, the oscillation input terminal O of the PLL circuit
The divided output d2 supplied to the SC has substantially the same frequency as the clock pulse ckr supplied to the reference frequency input terminal REF, and the clock pulse DV1 is
The frequency has four times the frequency of the clock pulse ck1. In FIG. 6, the PLL operation control signal P
It is shown as if the clock pulse DV1 of a stable frequency is being output immediately after the LLON or PLL standby signal PLLSB is set to the high level. It takes a relatively long time for the frequency of the clock pulse DV1 to stabilize.

As described above, the multiplexer MUX3
Selects the clock pulse ck1 having the lowest frequency and outputs it as the system clock signal CK1 when the clock enable signal CKEN is set to the high level and the selection control signal COSEL1 is set to the low level. When the clock enable signal CKEN is set to the high level and the selection control signal COSEL1 is set to the high level, the clock pulse DV1 is selected and output as the system clock signal CK1. As a result, the frequency of the system clock signal CK1 in the high-speed mode is
For example, the frequency is four times the frequency of the system clock signal CK1 in the low-speed mode.

In this embodiment, the clock enable signal CKEN is temporarily set to a low level prior to switching from the low-speed mode to the high-speed mode. When the clock enable signal CKEN is set to the low level, the output signal of the multiplexer MUX3, that is, the system clock signal CK1 is fixed at the low level, and the clock is stopped. As a result, hazard noise of the system clock signal CK1 due to the clock switching is eliminated, and the operation of the first internal circuit including the central processing unit CPU at the time of mode switching becomes stable, and the microprocessor and, consequently, the system including the same. Operation is stabilized.

FIG. 7 shows an example of an operation flow of the clock pulse generation circuit CPG of FIG. In the figure, when the microprocessor is in the low-speed mode in step ST1, the PLL control signal PLLON and the PLL standby signal PLLSB are both set to low level,
The voltage-controlled oscillator and the low-pass filter of the L circuit are made inoperative. Thus, the operation of the PLL circuit is stopped, and consumption of current excluding leak current can be prevented. At this time, each section of the microprocessor is formed based on a frequency-divided signal (clock pulse ck1) by the frequency-dividing circuit DIV1 of the oscillation pulse of the oscillation circuit XOSC or the pulse (clock pulse ckr) supplied from the external terminal EXTAL. The system clock signals CK1 and cks having a relatively low frequency are supplied. Accordingly, the central processing unit CPU and the like operate in the low-speed mode, and the power consumption of the entire microprocessor is reduced.

Next, in step ST2, when the occurrence of an event (event) requiring high-speed processing of the microprocessor is recognized (yes), the clock controller CKC sends a high-level PLL signal in step ST3.
A standby signal PLLSB is output, and P
The LL circuit is activated. In step ST4, PL
It is determined whether or not the frequency of the output signal of the L circuit is stable. If the stability of the frequency of the output signal is recognized (yes), then in step ST5, it is determined whether or not a high-speed processing request has been issued. Will be Needless to say, P
Until the frequency of the output signal of the LL circuit becomes stable, PL
The L circuit is set to the low-speed mode, that is, the activated state, and continues this state until a high-speed processing request is issued. During this time, the selection control signal COSEL1 remains at the low level, and the multiplexer MUX3 continues to output the low-speed mode system clock signal CK1 based on the clock pulse ck1. Therefore, the central processing unit CPU or the like continues to operate at a low speed. However, when an abnormality occurs in the system or when a data processing request to be performed in preference to the high-speed processing to be started is issued, the operation for that is performed. Can be started immediately, and unexpected situations can be dealt with.

In step ST5, when the request for starting the high-speed processing is recognized (yes), the selection control signal COSEL is selected by the clock controller CKC in step ST6.
1 is at a high level, and a system clock signal CK1 composed of a relatively high frequency clock pulse DV1 is supplied to a first internal circuit including the central processing unit CPU. As a result, the microprocessor enters the high-speed mode, and the central processing unit CPU and the like start high-speed processing.
Finally, in step ST7, the end of the high-speed processing is identified (yes).
s) When done, the microprocessor returns to the low speed mode.

In step ST4, if there is a request to start high-speed processing before the operation of the PLL circuit is recognized to be stable, this request is waited until the output frequency of the PLL circuit becomes stable. In this embodiment, as described above, before the selection control signal COSEL1 is changed to the high level, the clock enable signal CKEN is temporarily set to the low level, and the system clock signal CK1 is temporarily set to the clock stop state. However, since this time is extremely short, the central processing unit CP
The probability that U will not be able to cope with an unexpected situation is extremely small.

FIG. 8 shows a system configuration diagram of an embodiment of a microprocessor MPU incorporating the clock pulse generation circuit CPG of FIG. 1, and FIG. 9 shows a board layout diagram of the embodiment. ing. In FIG. 8, a microprocessor MPU includes a central processing unit CPU of a stored program system including an arithmetic unit ALU as a basic component. A multiplier MULT, a memory management unit MMU, and a cache memory CACHE are coupled to the central processing unit CPU via a system bus S-BUS, and an address translation table TLB is coupled to the memory management unit MMU. The memory management unit MMU and the cache memory CACHE are further coupled to a cache bus C-BUS on the other side, and a bus controller BSC is coupled to the cache bus C-BUS.

The bus controller BSC is connected to the peripheral bus P-BUS and the external bus E-BUS on the other side. The peripheral bus P-BUS includes a refresh controller REFC, a direct memory access controller DMAC, a timer circuit TIM, a serial communication interface SCI, a digital / analog conversion circuit D / A, and an analog / digital conversion circuit A / D. The device controller and the clock controller CKC are connected to each other, and the external interface EXIF is connected to the external bus E-BUS. The refresh controller REFC, the direct memory access controller DMAC, the timer circuit TIM, the serial communication interface SCI, the digital / analog conversion circuit D / A, and the analog / digital conversion circuit A / D are coupled to the interrupt controller INTC on the other side, and the interrupt is generated. Controller INTC is coupled to central processing unit CPU via interrupt request signal IRQ. Clock controller CK
A clock pulse generating circuit CPG and a plurality of clock switches to be described later are coupled to C, and a portable information terminal PDA, an external memory, and the like are coupled to the external interface EXIF.

A real-time clock circuit RTC is further connected to the interrupt controller INTC. This real-time clock circuit RTC is supplied with a clock signal of a stable frequency whose frequency does not change in accordance with each control signal of FIG. Thereby, the real-time clock circuit RTC performs accurate time management without being affected by the control signal. The real-time clock circuit RTC outputs an interrupt signal RTCI to the interrupt controller INTC at predetermined time intervals, and issues an interrupt request to the central processing unit CPU at predetermined time intervals. Note that an external interrupt signal OINT is also supplied to the interrupt controller INTC via a predetermined external terminal. Thus, the external device is logically coupled to the central processing unit CPU via the interrupt controller INTC.

In this embodiment, the clock controller CKC includes a plurality of control registers as described later. These control registers include a central processing unit CP.
From the U, predetermined control data is written or read via the peripheral bus P-BUS. The clock controller CKC controls the control signals PLLON, PLLSB, CO according to the control data set in each control register.
SEL1, COSEL2, CKEN, and the like are selectively formed, and a plurality of module enable signals ADEN, etc. described with reference to FIG. 10 are selectively formed. FIG.
Here, in order to avoid complicating the drawing, these control signals and module enable signals are shown by one line. Needless to say, the clock controller CKC
Instead of the peripheral bus P-BUS, a system bus S-BUS
May be combined.

Here, the central processing unit CPU operates in synchronization with the system clock signal CK1 supplied from the clock pulse generation circuit CPG, and executes predetermined arithmetic processing according to, for example, a control program read from the cache memory CACHE. , And controls and controls each unit of the microprocessor MPU. At this time, the arithmetic unit ALU executes an arithmetic and logic operation as needed, and the multiplier MULT executes a multiplication process. In addition, the memory management unit MMU converts a logical address output from the central processing unit CPU at the time of memory access into a physical address using the address conversion table TLB. Further, the cache memory CACHE is a memory that can be accessed at high speed, and reads and holds programs or data stored in an external memory provided outside the microprocessor MPU in a predetermined block unit, and Contributes to high-speed operation. Central processing unit CPU, multiplier MULT, memory management unit MM
U and the cache memory CACHE are so-called first internal circuits, and these circuits operate in accordance with a relatively high frequency system clock signal CK1.

The bus controller BSC controls the peripheral bus P-
It manages the bus access of each peripheral device controller coupled to the BUS and controls the operation of these peripheral device controllers. On the other hand, a refresh controller REFC, which is one of the peripheral device controllers, controls a refresh operation of a dynamic RAM (random access memory) provided as an external memory. Support high-speed data transfer to and from etc. Also, the timer circuit TIM
Supports time management required by the central processing unit CPU, and the serial communication interface SCI supports serial data transfer with an external communication control device or the like. Further, the analog / digital conversion circuit A / D converts an analog signal input from an external sensor or the like into a digital signal of a predetermined bit. The converted digital signal is converted into a predetermined analog signal and output to the outside.

The interrupt controller INTC alternatively receives an interrupt request from each peripheral device controller with a predetermined priority and transmits it to the central processing unit CPU as an interrupt request signal IRQ. The external interface EXIF controls and manages data transfer between each part of the microprocessor MPU and the externally connected portable information terminal PDA, external memory, and the like. Perform interface matching. The bus controller BSC and various peripheral device controllers are so-called second internal circuits, and these circuits operate in synchronization with a relatively low-frequency system clock signal cks.

In this embodiment, the components constituting the microprocessor MPU are arranged on a single semiconductor substrate SUB under a predetermined layout condition as shown in FIG. And selectively formed based on user specifications. Further, as described later, the microprocessor MPU of this embodiment includes a plurality of microprocessors provided corresponding to the plurality of modules and selectively turned on in response to the valid level of the corresponding module enable signal. A clock switch, and system clock signals CK1 and cks output from the clock pulse generation circuit CPG are:
After passing through the clock driver Driver, it is selectively supplied to each module via the corresponding clock switch. As a result, each module is selectively activated when necessary, thereby enabling the microprocessor MPU
Is further reduced in power consumption.

FIG. 10 shows the microprocessor M of FIG.
A connection diagram of one embodiment of a clock supply path in a PU is shown. In the figure, a clock pulse generation circuit C
The system clock signal CK1 of a relatively high frequency output from the multiplexer MUX3 in the PG passes through a predetermined clock driver and then passes through a first internal circuit via clock switches CS1 to CS4 (first selection circuit). First modules comprising a central processing unit CPU, a multiplier MULT, a memory management unit M
It is supplied to the MU and the cache memory CACHE. The clock switch CS1 outputs the module enable signal C
In response to the high level of PEN, the transmission state is selectively set,
Clock switches CS2, CS3 and CS4 are connected to corresponding module enable signals MUEN, TLEN or C
In response to the high level of AEN, each is selectively set to the transmission state. As a result, the central processing unit CPU, the multiplier MULT, the memory management unit MMU, and the cache memory CACHE receive the high level of the corresponding module enable signal and are selectively activated. The clock switch CS1 turned off by the module enable signal CPEN is turned on again by an external reset signal or an external interrupt signal (not shown).

Next, the system clock signal cks of a relatively low frequency output from the multiplexer MUX4 in the clock pulse generation circuit CPG passes through a predetermined clock driver Driver, and then changes to the clock switch CS5.
To a second module constituting a second internal circuit, ie, a bus controller B
SC, the refresh controller REFC, and the direct memory access controller DMAC.
After that, the timer circuit TIM, the interrupt controller INTC, the serial communication interface SCI, the digital / analog conversion circuit D / A, and the analog / digital conversion circuit A / D which are also the second internal circuits via the clock switches CS8 to CS12. Selectively supplied to

The clock switches CS5 to CS7 receive the high level of the corresponding module enable signal BCEN, RCEN or DMEN, and are selectively brought into a transmission state, respectively. , U
Upon receiving the high level of AEN, DAEN or ADEN, the transmission state is selectively set. As a result, the bus controller BSC, the refresh controller REFC,
The direct memory access controller DMAC, timer circuit TIM, interrupt controller INTC, serial communication interface SCI, digital / analog conversion circuit D / A, and analog / digital conversion circuit A / D receive the corresponding module enable signal at a high level, respectively. The operation state is selectively set.

As described above, each unit in the microprocessor MPU is modularized, and the system clock signal CK1
Alternatively, by selectively supplying cks to each module in accordance with the module enable signal, it is possible to selectively separate unnecessary modules in the system configuration and to operate the modules not used according to the processing contents of the microprocessor. It can be selectively stopped to prevent useless current consumption. That is, each module is selectively put into operation according to the processing content of the microprocessor MPU, thereby reducing the power consumption of the microprocessor MPU and the applied system.

Note that even when the corresponding clock switch is turned on and the system clock signal CK1 is supplied to each module, the system clock signal CK1 receives the control signal COSEL1 (C
The frequency is selectively switched according to OSEL2). That is, when the microprocessor MPU is in the low-speed mode and the selection control signal COSEL1 is at the low level, the system clock signal CK1 is formed in accordance with the clock pulse ck1 having a relatively low frequency. When the signal COSEL1 is set to the high level, the signal COSEL1 is formed in accordance with the clock pulse DV1 having a frequency four times that of the signal COSEL1. Therefore, for a process that does not require a high-speed operation, the frequency of the system clock signal CK1 can be selectively reduced by the control signal COSEL1, and the process can be performed while preventing unnecessary current consumption. . That is, in this embodiment, the operation of the first internal circuit including the central processing unit CPU is selectively made faster or slower in accordance with the processing content, and the processing capability of the microprocessor MPU is changed in accordance with the occurrence of an event or the like. Can be selectively switched.

Further, in this embodiment, when the microprocessor MPU is switched from the low-speed mode to the high-speed mode, the clock enable signal CKEN is temporarily set to the low level, and in response to this, the system clock signal CKEN is received.
K1 is temporarily brought into the clock stop state. As a result,
Hazard noise caused by mode switching can be prevented, and the operation of each unit of the microprocessor MPU can be stabilized.

FIG. 11 shows the microprocessor M of FIG.
A block diagram of one embodiment of a clock controller CKC (controller) included in a PU is shown. In the figure, the clock controller CKC has two control registers CPG-Reg and CS-
Reg and a clock controller control circuit CTL (control circuit). Among them, the control register CPG-R
eg is a control signal PLLON, PLLSB, COSEL for switching the frequency of the system clock signal CK1.
1, a plurality of bits corresponding to COSEL2 and CKEN, and a peripheral bus P-BU from the central processing unit CPU.
It receives writing or reading of control data via S and the clock controller control circuit CTL. The control register CS-Reg has a module enable signal C
PEN, MUEN, TLEN, CAEN, BCEN, R
CEN, DEN, TTEN, IKEN, UAEN, D
It includes a plurality of bits corresponding to AEN and ADEN, and similarly receives writing or reading of control data from the central processing unit CPU via the peripheral bus P-BUS and the clock controller control circuit CTL. Further, the clock controller control circuit CTL includes a peripheral bus P-BUS
That is, the central processing unit CPU and the control register CPG
-Reg or CS-Reg, and selectively forms a corresponding control signal or module enable signal based on control data set in each bit of these control registers.

Next, an outline of the operation of the clock controller CKC will be described. Although not shown in FIG. 11, the control register CPG-Reg includes the control signal PLLON,
PLLSB, COSEL1, COSEL2 and CKEN
(Bon), (Bsb),
(Bl1), (Bl2) and (Ben),
Control data for a corresponding control signal is selectively set in each bit. The control data is set by the central processing unit CPU specifying the control register CPG-Reg via the peripheral bus P-BUS and writing control data of logic "1" or "0" to the corresponding bit. Achieved.

Although not particularly limited, the central processing unit C
A predetermined address is assigned to the control register CPG-Reg so that the PU can specify the control register CPG-Reg. Further, the clock controller control circuit CTL selectively forms a corresponding control signal according to the control data set in each bit of the control register CPG-Reg. That is, for example, when the central processing unit CPU writes the control data of logic “1” to the bit (Bon) in the control register CPG-Reg, the clock controller CKC outputs the control signal PLLO
N is set to high level. On the other hand, when the central processing unit CPU writes the control data of logic “0” to the bit (Bon), the clock controller control circuit CT
L sets the control signal PLLON to low level. Similarly, the central processing unit CPU sets the register CPG-Reg.
Bit (Bsb), (Bl1), (Bl2) or (B
When the control data of logic “1” or “0” is written to the corresponding control signal PLLSB, COSEL1, COSEL2,
Alternatively, CKEN is selectively set to a high level or a low level, respectively.

On the other hand, the control register CS-Reg
1, the module enable signal C
PEN, MUEN, TLEN, CAEN, BCEN, R
CEN, DEN, TTEN, IKEN, UAEN, D
Bit (Bc) corresponding to each of AEN and ADEN
p), (Bmu), (Btl), (Bca), (Bb
c), (Brc), (Bdm), (Btm), (Bi
c), (Bua), (Bda) and (Bad), and control data relating to the corresponding module enable signal is selectively set in these bits.
These sets of control data are stored in the central processing unit CP.
U receives the control register CS-R via the peripheral bus P-BUS.
This is achieved by designating an eg and selectively writing control data of logic "1" or "0" to the corresponding bit.

Although not particularly limited, the central processing unit C
A predetermined address is assigned to the control register CS-Reg so that the PU can specify the control register CS-Reg. Further, the clock controller control circuit CTL selectively forms a corresponding module enable signal according to control data set in each bit of the control register CS-Reg. That is, for example, the central processing unit CPU sets the control register CS-Re
When the control data of logic “1” is written to the bit (Bmu) in “g”, the clock controller control circuit CTL
Sets the corresponding module enable signal MUEN to high level. In contrast, the central processing unit CPU
Writes the control data of logic “0” to the bit (Bmu), the clock controller control circuit CTL sets the module enable signal MUEN to low level.
Similarly, the central processing unit CPU determines the bit (Bcp),
(Btl), (Bca), (Bbc), (Brc),
(Bdm), (Btm), (Bic), (Bua),
When the control data of logic “1” or “0” is written to (Bda) or (Bad), respectively, the clock controller control circuit CTL causes the corresponding module enable signals CPEN, TLEN, CAEN, BCEN, RC
EN, DDEN, TTEN, IKEN, UAEN, DA
EN or ADEN is selectively set to a high level or a low level, respectively.

In this embodiment, the clock controller control circuit CTL further has a function of receiving the control signal RST from the interrupt controller INTC and forcibly resetting each bit of the control register CS-Reg. This reset causes the control register CS-
Each bit of Reg is set to control data "1" which makes the clock switch conductive.

The writing (setting) of control data to each bit of the control register CPG-Reg by the central processing unit CPU is instructed, for example, by a program executed by the central processing unit CPU. Accordingly, by including a predetermined instruction in the program, the frequency of the system clock signal in the microprocessor MPU can be switched by software. As described above, the switching of the frequency of the system clock signal can also be realized by inputting a predetermined switching control signal from the external terminals CKEXT and CKRATE. As a result, the frequency of the system clock signal can be determined from the external terminals CKEXT and CKRATE, for example, even before the program is executed (for example, in an initial state after reset).

FIGS. 12A, 12B and 12
FIG. 8C is a conceptual diagram of one embodiment of an application example that requires switching of the processing speed in the microprocessor MPU of FIG. In these examples,
The microprocessor MPU is provided to a personal digital assistant PDA provided with an input pen and becomes a central device thereof. The portable information terminal PDA includes an LCD (liquid crystal display) with a pressure-sensitive sheet, and the operator writes characters on the LCD with the pressure-sensitive sheet with an input pen to allow the portable information terminal PDA to be written.
Input to. The tip of the input pen is provided with a microswitch (not shown) for identifying that the operator is pressing the LCD against the pressure-sensitive sheet and writing some characters, and the open / closed state of the switch is set. , To the microprocessor MPU via a signal path (not shown). The microprocessor MPU identifies the state of the input pen based on this, and recognizes the occurrence of an event requiring high-speed processing and the request for starting high-speed processing in FIG.

That is, as shown in FIG. 12A, when the input pen is placed outside the LCD with the pressure-sensitive sheet and characters are not written by the operator, the micro switch of the input pen is turned off. Then, the microprocessor MPU receives the request and the portable information terminal PDA
Is in a standby state. Then, instructing the clock controller CKC, the PLL operation control signal PLLO for the clock pulse generation circuit CPG of FIG.
N and the PLL standby signal PLLSB are set to low level, the clock enable signal CKEN is set to high level, and the selection control signal COSEL1 is set to low level. As a result, the PL of the clock pulse generation circuit CPG is
The L circuit is brought into an operation stop state, its power consumption is reduced, the frequency of the system clock signal CK1 is lowered, and the first internal circuit including the central processing unit CPU operates at low speed with low power consumption. The instruction to the clock controller CKC in FIG. 12A is based on bits (Bon) and (Bs) in the control register CPG-Reg.
This is achieved by writing control data "0" to b) and (B11) and writing control data "1" to bit (Ben). That is, a program for writing such control data is stored in the central processing unit C.
That is, the instruction is given by causing the PU to execute.

Next, as shown in FIG. 12B, when the operator presses the input pen on the LCD with the pressure-sensitive sheet to start writing characters, the micro switch of the input pen is turned on, and the microprocessor is turned on. MPU is
In response to this, a high-speed event, that is, an event requiring a high-speed processing is recognized. Then, it instructs the clock controller CKC to set the PLL standby signal PLLSB for the clock pulse generation circuit CPG to high level, and to activate the PLL circuit. At this time, the selection control signal COSEL1 is kept at the low level as described above, and the first internal circuit including the central processing unit CPU continues the low-speed operation. The instruction to the clock controller CKC in FIG.
This is achieved by writing the control data “0” to the bits (Bon) and (B11) in the G-Reg and writing the control data “1” to the bits (Bsb) and (Ben). That is, the instruction is issued by causing the central processing unit CPU to execute a program for writing such control data. It should be noted that writing to the control register CPG-Reg may be performed only for the contents of the control register CPG-Reg, that is, only for bits whose control data is changed. The writing of the control data “1” to the bit (Bsb) of the control register CPG-Reg for turning on the PLL circuit is performed by the control register CP.
This can be replaced with writing of control data “1” for the G-Reg bit (Bon).

On the other hand, as shown in FIG. 12C, when the operator finishes writing one character and releases the input pen from the LCD with the pressure-sensitive sheet, the micro switch of the input pen is turned off again. Microprocessor MPU
Recognizes the request for starting the high-speed processing in response to the request. Then, the clock controller CKC is instructed to temporarily set the clock enable signal CKEN supplied to the clock pulse generation circuit CPG to a low level, and then set the selection control signal COSEL1 to a high level. As a result, the frequency of the system clock signal CK1 is increased, for example, by four times, and the first internal circuit including the central processing unit CPU shifts to the high-speed mode. Needless to say, at this time, the PLL circuit of the clock pulse generation circuit CPG is in a stable state, and the central processing unit CPU analyzes the character written by the operator based on the character data sent from the LCD with the pressure-sensitive sheet. Can be done at high speed.

The instruction to the clock controller CKC in FIG. 12C is not particularly limited.
It is performed in substantially two stages. That is, first, in order to temporarily set the clock enable signal CKEN to the low level, the bit (Be
Control data “0” is written to n). Then, when a predetermined time has elapsed, the control register CPG-Reg
The control data "1" is written to the bits (Ben) and (Bl1) in the
KEN is set to the high level again, and the selection control signal COSEL1 is set to the high level. Needless to say, these instructions are realized by causing the central processing unit CPU to execute a program for writing control data in two stages. Control register C
Writing to the PG-Reg may be selectively performed only on bits whose contents are changed.

The frequency of the system clock signal cks supplied to the peripheral circuit can be changed by writing the control data to the bit (B12) as described above. That is, for example, at the time of the instruction in FIG. 12A, the control data “0” is written to the bit (B12) in the control register CPG-Reg,
At the time of the instruction in FIG. 2 (B) and FIG. 12 (C), the control data “1” is written to the bit (B12). Thus, in the standby state shown in FIG.
12 (B) and FIG.
This is lower than the state in (C), whereby the power consumption of the peripheral circuits in the standby state can be reduced. Of course,
Writing of control data to the bit (B12) is instructed by a program. That is, the frequency of the system clock signal cks is equal to the system clock signal CK1.
12 (A) and (B).
And (C) may be changed at any time, or may not be changed at all.

In the operation flow shown in FIG. 7, each of steps ST1, ST3 and ST6 is as described above.
This is realized by executing a program for writing control data to the control register CPG-Reg. That is, in step ST4, for example, the time from when the PLL circuit is activated to when its output stabilizes is obtained in advance, and this is determined by the timer circuit TIM and the real-time clock circuit RTC.
Etc. In step ST3, the control register CP
After writing the control data into the G-Reg, for a predetermined time set in the timer circuit TIM or the like, for example, even if there is a high-speed processing request in step ST5, the program corresponding to step ST6 need not be executed. . Thereby, the processing of steps ST4 and ST5 is realized.

In step ST7, a program for analyzing characters written by the input pen is executed by the central processing unit CPU. When the character analysis is completed, the predetermined control data is written into the control register CPG-Reg, and the process returns to the standby state of step ST1. Further, in each of steps ST2 and ST5, for example, a program for reading the state of the microswitch of the input pen into the central processing unit CPU via the external interface EXIF is prepared, or an interrupt signal is generated when the state of the microswitch changes. This is realized by preparing an interrupt processing program for receiving the interrupt signal and checking the state of the microswitch. As mentioned above,
The operation flow shown in FIG. 7 is executed by executing a corresponding predetermined program by the central processing unit CPU.
This is achieved by software.

Note that P of the clock pulse generation circuit CPG is
The time from the activation of the LL circuit to the stabilization of its output frequency is about milliseconds, which is sufficiently shorter than the time from the start of writing of the character by the operator to the end thereof. Therefore, when the request for starting the high-speed processing in FIG. 12C is recognized by the microprocessor MPU and the mode switching is performed, the output frequency of the PLL circuit is in a sufficiently stable state, No meeting occurs.

FIG. 13A and FIG. 13B show FIG.
1 is a conceptual diagram of one embodiment for explaining the effect of switching the processing speed in the microprocessor MPU. FIG. 13A shows an operation of switching the processing speed in the microprocessor for executing the flow shown in FIG. 19 in order to facilitate understanding of the present invention, and FIG. The figure shows a comparison of the switching operation of the processing speed in the microprocessor of the present invention.

Referring to FIG. 13B, in the microprocessor MPU of the present invention, as described above, when the occurrence of the high-speed event, that is, the event requiring the high-speed processing is recognized, the PLL standby signal PLLSB is set to the high level. Then, the PLL circuit of the clock pulse generation circuit CPG is activated. In the state of waiting for stabilization until the output frequency of the PLL circuit is stabilized, the system clock signal CK1 is formed according to the clock pulse ck1 having a relatively low frequency as in the low-speed mode, and the first internal clock including the central processing unit CPU The circuit continues low speed processing.

Next, when the microprocessor MPU recognizes the request for starting the high-speed processing, the clock enable signal CKEN is temporarily set to the low level, and the system clock signal CK1 is temporarily stopped. Thereafter, when the clock enable signal CKEN is returned to the high level and the selection control signal COSEL1 is changed to the high level, the frequency of the system clock signal CK1 is increased, for example, by four times as compared with that in the low-speed mode, and the central processing is performed. The first internal circuit including the unit CPU shifts to the high-speed mode, and its processing capacity is increased.

On the other hand, in the case of a microprocessor executing the operation flow of FIG. 19, as shown in FIG. 13A, the PLL circuit of the clock pulse generation circuit is activated when a request for starting high-speed processing is recognized. The system clock signal is stopped until the output frequency is stabilized. For this reason, a relatively long time is required from when the request for the start of the high-speed processing is recognized until the microprocessor MPU shifts to the high-speed mode, and while the system clock signal is stopped, the microprocessor MPU is about to execute the request. When an emergency process such as a process having a higher priority than a process or a failure occurs, the microprocessor MPU cannot cope with this. In other words, the microprocessor MPU goes into a system down state.

As in this embodiment, when the occurrence of a high-speed event is recognized, the PLL circuit of the clock pulse generation circuit CPG is first activated, and the central processing unit CPU and the like are also used until the output frequency of the PLL circuit is stabilized. At a low speed, and when the request for the start of the high-speed processing is recognized, the mode can be immediately shifted to the high-speed mode, so that the mode switching operation of the microprocessor MPU can be sped up. A microprocessor capable of coping with the occurrence of emergency processing such as a failure can be realized and its reliability can be improved.

When the microprocessor of the present invention is used in the above-mentioned portable information terminal PDA, the occurrence of an event requiring high-speed processing can be recognized according to the state of the microswitch of the input pen. It can be predicted that character pattern recognition processing that requires high-speed processing will be required. Therefore, it is effective to activate the PLL circuit of the clock pulse generation circuit CPG to set the standby state when the start of character writing is recognized as the occurrence of a high-speed event.

FIG. 14 partially shows an example of a data transmission path between the modules of the microprocessor of FIG. In the figure, for example, a multiplier MULT
Has an input register IREG coupled to a 32-bit data bus SBD0 to SBD31 forming a system bus S-BUS, and the input register IREG is provided corresponding to each bit of the data bus SBD0 to SBD31. It has 32 unit latch circuits ULT. Each of these unit latch circuits ULT includes a so-called static latch in which a pair of inverters V3 and V4 are cross-coupled, as represented by the 0th bit. The input / output node of this static latch is connected to a data bus S via a clocked inverter CV1.
The bits are coupled to the corresponding bits of BD0 to SBD31, and after their levels are inverted by inverter V5, they become internal input data ID0 to ID31.

The control terminal of the clocked inverter CV1 forming each unit latch circuit ULT of the input register IREG is commonly supplied with the output signal of the AND gate AG7 forming the clock switch CS2 of FIG.
One input terminal of the AND gate AG7 is supplied with the output signal of the multiplexer MUX3 of the clock pulse generation circuit CPG, that is, the system clock signal CK1, and the other input terminal is provided with the module enable signal MUE.
N is supplied. As a result, the output signal of the AND gate AG7 is selectively set to the high level by setting both the module enable signal MUEN and the system clock signal CK1 to the high level.
7 receives the high level of the output signal of each unit latch circuit U.
LT clocked inverter CV1 is selectively set to the transmission state.

As described above, the system clock signal CK
1, the frequency is selectively switched according to the selection control signal COSEL1, and the clock enable signal CKEN is set to a low level to be temporarily stopped. Further, the output signal of the AND gate AG7 is selectively stopped by the module enable signal MUEN being set to low level.
However, each unit latch circuit UL of the input register IREG
T is, as described above, a system clock signal C since it includes a static latch as a basic configuration.
The frequency of K1 is selectively switched and AND gate AG
Even if the output signal of No. 7 is stopped, data can be held stably and this can be dealt with.

FIG. 15 shows the microprocessor M of FIG.
An example of a data transmission path from the high-speed module to the low-speed module in the PU is partially shown, and FIG. 16 shows a signal waveform of an example of the data transmission path shown in FIG. FIG. 17 shows an example of a data transmission path from the low-speed module to the high-speed module of the microprocessor MPU in FIG. 8, and FIG. 18 shows a signal waveform of an example of the data transmission path shown in FIG. Have been. The high-speed module includes a central processing unit CPU, a multiplier MULT, and a memory management unit MMU.
And a first internal circuit including a cache memory CACHE, and FIG. 15 to FIG. 18 show a memory management unit MMU as a typical example. The low-speed module means a second internal circuit including the bus controller BSC and various peripheral device controllers, and the bus controller BSC is shown as a representative example in FIGS. Further, according to the signal waveforms of FIGS. 16 and 18, the system clock signal CK1 and the system clock signal cks
Is set to four times.

In FIG. 15, a memory management unit MMU, which is a high-speed module, has a 32-bit data bus CB whose output terminal forms a cache bus C-BUS.
An output register OREG coupled to D0-CBD31, the output register OREG being connected to a data bus CB.
32 provided corresponding to each bit of D0 to CBD31
It includes the unit latch circuits ULT. A data input terminal of each unit latch circuit ULT has a memory management unit MM.
The corresponding internal output data DO0 to DO31 is supplied from a preceding stage circuit (not shown) of U, and its clock input terminal c
The output signal of the AND gate AG8 is commonly supplied to k. The unit latch circuit ULT forming the output register OREG is formed of a static latch having the same configuration as the unit latch circuit ULT forming the input register IREG in FIG. Therefore, the specific configuration is not shown in FIG.

The set signal SSET is supplied to the first input terminal of the AND gate AG8 of the memory management unit MMU. The second input terminal is supplied with the system clock signal CK1, and the third input terminal is supplied with the inverted ready signal / BRDY from the multi-clock controller MCKC. Set signal SSET
Is also supplied to the multi-clock controller MCKC, which is further supplied with system clock signals CK1 and cks from the clock pulse generation circuit CPG.

On the other hand, the bus controller BSC, which is a low-speed module, has its input terminals connected to data buses CBD0 to CBD.
An input register IREG coupled to the BD 31;
This input register IREG has data buses CBD0 to CBD.
It has 32 unit latch circuits ULT provided corresponding to each bit of the BD 31. The data input terminal of each unit latch circuit ULT is connected to the corresponding data bus CBD0-CB.
D31 respectively, and its clock input terminal CK
Are commonly supplied with the output signal of the AND gate AG9. The unit latch circuit ULT constituting the input register IREG has the same configuration as the unit latch circuit ULT shown in FIG.

AND gate A of bus controller BSC
One input terminal of G9 is supplied with a request signal MRQS from the multi-clock controller MCKC, and the other input terminal is supplied with a system clock signal cks.

Although not particularly limited, the internal output data DO0 to DO3 are output from the preceding circuit in the memory management unit MMU.
When 1 is output, as shown in FIG. 16, the set signal SSET goes high in response to the falling edge of the system clock signal CK1. Therefore, at the first rising edge of the system clock signal CK1, the output signal of the AND gate AG8 changes to a high level, and the internal output data DO0 to DO31 are stored in the memory management unit MM.
The data is taken into the output register OREG of U and outputted to the data buses CBD0 to CBD31 of the cache bus C-BUS. In response to the high level of the set signal SSET and the rising edge of the system clock signal CK1, the request signal MRQS is set to the high level, and the ready signal / BRDY is set to the low level. In response to the high level of the request signal MRQS, the system clock signal cks becomes an output signal of the AND gate AG9, and is supplied to the unit latch circuit ULT constituting the input register IREG of the bus controller BSC. The data on CBD0 to CBD31 is taken into the input register IREG. The data taken into the input register IREG is transmitted to the bus controller B
This is transmitted to the SC internal circuit.

Input register I of bus controller BSC
When the data acquisition to the REG is completed, first, the request signal MRQS is returned to the low level in response to the low level of the inverted ready signal / BRDY and the rising edge of the system clock signal cks, and the request signal MRQS is returned to the low level in response to the low level of the request signal MRQS and the system clock signal cks. Receiving falling edge, inverted ready signal / BRDY
Is returned to the high level. Also, the inverted ready signal / BR
In response to the high level of DY and the falling edge of the system clock signal CK1, the set signal SSET is returned to low level, and the data transmission path is returned to the initial state.

From these, the memory management unit M
In the MU, the incorporation of the internal output data DO0 to DO31 into the output register OREG corresponds to the inversion ready signal / B
In response to the low level of RDY, the system clock signal CK
1 is limited to one rising edge, and the inverted ready signal / BRDY is supplied to the data buses CBD0 to CBD31 by the input register IREG of the bus controller BSC.
After the above data has been fetched, it is returned to the high level with a sufficient timing margin. Therefore,
Memory management unit MMU and bus controller BSC
Are different from the system clock signals CK1 and ck
Despite the operation according to s, the data transfer between the two is performed reliably, and the operation is stabilized.

Next, in the case of FIG. 17, the bus controller BSC, which is a low-speed module, has a 32-bit data bus C whose output terminal forms the cache bus C-BUS.
Output register OREG coupled to BD0 to CBD31
And the output register OREG is connected to the data bus C
3 provided corresponding to each bit of BD0 to CBD31
It has two unit latch circuits ULT. A data input terminal of each unit latch circuit ULT has a bus controller BS.
C, corresponding internal output data DO0 to DO31 are supplied from a preceding stage circuit (not shown), and a clock input terminal c
The output signal of the AND gate AG10 is commonly supplied to k. The unit latch circuit ULT constituting the output register OREG is the same as the input register IREG shown in FIG.
Has the same configuration as that of the unit latch circuit ULT.

AND gate A of bus controller BSC
A set signal SSET is supplied to a first input terminal of G10. Further, the system clock signal cks is supplied to the second input terminal, and the third input terminal is supplied to the third input terminal.
An inverted ready signal / BRDY is supplied from the multi-clock controller MCKC. The set signal SSET is also supplied to a multi-clock controller MCKC, and the multi-clock controller MCKC further receives a system clock signal c from a clock pulse generation circuit CPG.
ks and CK1 are supplied.

On the other hand, the memory management unit MMU, which is a high-speed module, has its input terminals connected to the data buses CBD0 to CBD0.
It has an input register IREG coupled to CBD 31, which is connected to data bus CBD0.
To CBD 31 are provided for 32 unit latch circuits ULT. The data input terminals of these unit latch circuits ULT are connected to corresponding data buses CB.
The output signals of the AND gate AG11 are commonly supplied to clock input terminals CK of the D0 to CBD31. The unit latch circuits ULT forming the input register IREG have the same configuration as the unit latch circuits ULT forming the input register IREG in FIG.

The request signal MRQS is supplied from the multi-clock controller MCKC to one input terminal of the AND gate AG11 of the memory management unit MMU, and the system clock signal CK is supplied to the other input terminal.
1 is supplied.

Although not particularly limited, the bus controller B
The internal output data DO0 to DO31 from the preceding circuit in the SC
Is output, the set signal SSET is set to the high level in response to the falling edge of the system clock signal cks, as shown in FIG. Therefore, at the first rising edge of the system clock signal cks, the output signal of the AND gate AG10 changes to a high level, and the internal output data DO0 to DO31 are transmitted to the bus controller BSC.
And output to the data buses CBD0 to CBD31 of the cache bus C-BUS. In response to the high level of the set signal SSET and the next falling edge of the system clock signal cks, the request signal MRQS is set to the high level, and the ready signal / BRDY is set to the low level. In response to the high level of the request signal MRQS, the system clock signal CK1 is supplied to the unit latch circuit ULT constituting the input register IREG of the memory management unit MMU via the AND gate AG11. The data on the CBD 31 is taken into the input register IREG. Input register IR
The data taken into the EG is stored in the memory management unit MM.
It is transmitted to the internal circuit in U.

When the data has been taken into the input register IREG of the memory management unit MMU, the request signal MRQS is first returned to the low level in response to the low level of the inverted ready signal / BRDY and the next rising edge of the system clock signal CK1, The set signal SSET is returned to the low level in response to the low level of the request signal MRQS and the ready signal / BRDY and the next rising edge of the system clock signal cks. In response to the low level of the set signal SSET and the falling edge of the system clock signal CK1, the inverted ready signal / BRDY is returned to the high level, and the data transmission path is returned to the initial state.

From these, the memory management unit M
In the MU, the incorporation of the internal output data DO0 to DO31 into the output register OREG corresponds to the inversion ready signal / B
Receiving the low level of RDY, the system clock signal ck
s, and the inverted ready signal / BRDY is supplied to the data buses CBD0 to CBD3 by the input register IREG of the memory management unit MMU.
After the data on the first data has been fetched, the signal is returned to the high level with a sufficient timing margin. Therefore, the bus controller BSC and the memory management unit M
Although the MU operates in accordance with the system clock signals cks and CK1 having different frequencies, data transmission and reception between the two are reliably performed, and the operation is stabilized.

Although not particularly limited, the set signal SSET is formed by a module that outputs data.

The operation and effect obtained from the above embodiment are as follows. That is, (1) In a microprocessor having a built-in PLL circuit that forms a relatively high-frequency oscillation pulse obtained by multiplying a clock pulse of a relatively low frequency as a reference frequency input, the operation of the PLL circuit is stopped in the low-speed mode And outputs a system clock signal corresponding to a clock pulse of a relatively low frequency. In the high-speed mode, the PLL circuit is first activated upon occurrence of an event requiring high-speed processing, and then the PLL circuit is stabilized and operates at a high speed. Until there is a request for processing start, the system clock signal corresponding to the above-mentioned relatively low frequency clock pulse is continuously output, and when the output frequency of the PLL circuit is stabilized and a request for starting high-speed processing is made. And a system clock signal corresponding to a relatively high frequency oscillation pulse formed by a PLL circuit. By outputting the signal, the microprocessor can be switched from the low-speed mode to the high-speed mode at high speed.

(2) According to the above item (1), the operation of the microprocessor can be continued until the output frequency of the PLL circuit is stabilized. The effect that can be obtained is obtained. (3) According to the above item (2), an effect is obtained that the reliability of the microprocessor can be increased while reducing the power consumption of the microprocessor.

(4) In the above items (1) to (3), when switching from the low-speed mode to the high-speed mode, the system clock signal is temporarily stopped for an extremely short time to reduce the hazard noise accompanying the clock switching. This has the effect that the operation of the microprocessor can be stabilized when switching the mode. (5) In the above items (1) to (4), the components of the microprocessor are modularized, and a system clock signal is selectively supplied to each module in accordance with a corresponding module enable signal. Modules that have become unused can be selectively disconnected, and the operation of modules that are not used in accordance with the processing content of the microprocessor can be selectively stopped,
The effect of promoting low power consumption of the microprocessor can be obtained.

(6) In the above items (1) to (5), data transmission and reception between modules operating in response to system clock signals of different frequencies may be performed, for example, by using a static latch including a pair of cross-coupled inverters. By doing so, it is possible to prevent data loss when the system clock signal is switched or when the clock is stopped, and to obtain an effect that the operation of the microprocessor can be further stabilized. (7) By using the microprocessor of the above items (1) to (6) for a portable information terminal or the like including an input pen, the power consumption of the microprocessor and thus the portable information terminal can be reduced and the operation thereof can be stabilized. The effect is obtained. (8) Since a module to supply a system clock signal can be selected by a module enable signal and the frequency of the system clock signal can be changed, necessary processing can be performed with low power consumption. (9) By writing predetermined control data into the control register, the frequency of the system clock signal can be changed, and the module to which the system clock signal is to be supplied can be selected, so that the flexibility of the microprocessor can be increased.

The invention made by the present inventor has been specifically described based on the embodiment. However, the invention of the present application is not limited to the above embodiment, and can be variously modified without departing from the gist of the invention. Needless to say. For example, in FIG. 1, a clock generation circuit for forming a system clock signal of a relatively high frequency based on a clock pulse of a relatively low frequency does not necessarily have to be a PLL circuit in particular. The circuit XOSC is not limited to the one using the crystal oscillator. The number of phases of each clock pulse and system clock signal can be set arbitrarily, and the block configuration of the clock pulse generation circuit CPG is also arbitrary.

FIG. 2, FIG. 3 (A), FIG. 3 (B), FIG.
The configurations of the PLL circuits shown in FIGS. 4A and 4B are not restricted by these embodiments. FIG. 5 (A), FIG.
In (B), various embodiments can be considered for the logical configuration of the multiplexers including the MUX3 and the MUX4. In FIG. 6, the phase relationship and the frequency relationship between each clock pulse and the system clock signal are not restricted by this embodiment, and the clock enable signal CKEN is used.
The same applies to the effective levels of the selection control signals COSEL1 and COSEL2. System clock signal CK
When the frequencies of 1 and cks can be switched without hazard noise, there is no need to provide a clock stop period. In FIG. 7, if it can be ensured that the output frequency of the PLL circuit is stabilized without any problem between the start of the PLL circuit and the start of high-speed processing, the determination in step ST4 can be omitted.

In FIG. 8, the microprocessor MPU
Can take any block configuration, and its bus form is also arbitrary. The board layout shown in FIG. 9 is only an example, and does not limit the present invention. In FIG. 10, the second internal circuit including the bus controller BSC includes 1
The system clock signal cks may be supplied via one or three or more clock drivers. FIG.
In 1, the clock controller CKC may include an arbitrary number of control registers, and its block configuration and connection form may take various embodiments.

In FIG. 12, a method of recognizing a high-speed event occurrence and a high-speed processing start request in the portable information terminal PDA can be arbitrarily selected. For example, the start of writing a character may be recognized as the occurrence of a high-speed event, and the time when a predetermined area on the input screen is designated with the input pen may be recognized as a request for starting high-speed processing. The appearance structure of the portable information terminal PDA is not restricted by this embodiment. FIG.
13A and 13B, the time relationship between the processing stages at the time of mode switching is not absolute. In FIG. 14, the configuration of the unit latch circuit ULT included in the input register IREG and the like can take various embodiments. In FIG. 15 and FIG.
The control method of the input register IREG is not limited, and the timing relationship and the effective level of each signal shown in FIGS. 16 and 18 are also arbitrary.

In the above description, the case where the invention made by the inventors of the present application is applied to a microprocessor having a built-in PLL circuit and a portable information terminal including the same, which is a field of application, has been described. The present invention is not limited thereto. For example, the present invention can be applied to microprocessors incorporating various clock generation circuits and various systems using these microprocessors.
INDUSTRIAL APPLICABILITY The present invention can be widely applied to a microprocessor having at least a clock pulse generating circuit and having a plurality of operation modes according to system clock signals of different frequencies, and an apparatus and a system including such a microprocessor.

[0111]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a microprocessor incorporating a PLL circuit that forms a relatively high-frequency oscillation pulse obtained by multiplying a clock pulse of a relatively low frequency as a reference frequency input and multiplying the same by a reference frequency, in a low-speed mode, P
The operation of the LL circuit is stopped to output a system clock signal corresponding to a clock pulse of a relatively low frequency. In the high-speed mode, the PLL circuit is first activated upon receiving an event requiring high-speed processing, and then the PLL circuit is activated. Until the circuit is stable and there is a request to start high-speed processing, a system clock signal corresponding to the above-mentioned relatively low-frequency clock pulse is continuously output, so that the output frequency of the PLL circuit is stable and high-speed processing starts. PLL when requested
By outputting a system clock signal corresponding to a relatively high-frequency oscillation pulse formed by the circuit, the microprocessor switches from the low-speed mode to the high-speed mode at a high speed when a request for high-speed processing is requested. And at the same time, continuously supply a system clock signal corresponding to the low-speed mode at the time of such switching,
Since the operation of the microprocessor can be continued, it is possible to cope with an unexpected situation such as occurrence of a priority process or a failure. As a result, it is possible to realize a microprocessor that switches from the low-speed mode to the high-speed mode at a high speed and has a function that can cope with an unexpected situation even when the mode is switched.

When switching from the low-speed mode to the high-speed mode, by temporarily stopping the system clock signal for a very short time, it is possible to prevent hazard noise due to the clock switching, so that the microprocessor is not required to switch the mode. The operation can be further stabilized and its reliability can be increased.

By modularizing each part of the microprocessor and selectively supplying a system clock signal to each module in accordance with the module enable signal, it is possible to selectively separate modules that are unnecessary in the system configuration, The operation of a module that is not used is selectively stopped according to the processing content of the processor, so that the power consumption of the microprocessor can be reduced.

Data transfer between modules operating in response to system clock signals of different frequencies is performed via a static latch including a pair of cross-coupled inverters, so that the system clock signal can be switched or the clock can be stopped. Can prevent data loss and stabilize the operation of the microprocessor.

By using such a microprocessor in a portable information terminal or the like having an input pen, the operation of the microprocessor and the portable information terminal can be stabilized while reducing the power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a clock pulse generation circuit built in a microprocessor according to the present invention.

FIG. 2 shows a PL included in the clock pulse generation circuit of FIG. 1;
FIG. 3 is a block diagram showing one embodiment of an L circuit.

FIG. 3 is a partial circuit diagram showing one embodiment of the PLL circuit of FIG. 2;

FIG. 4 is another partial circuit diagram showing one embodiment of the PLL circuit of FIG. 2;

FIG. 5 is a circuit diagram showing one embodiment of two types of multiplexers included in the microprocessor of FIG. 1;

FIG. 6 is a signal waveform diagram showing one embodiment of the clock pulse generation circuit of FIG. 1;

FIG. 7 is a flowchart showing an operation of the clock pulse generation circuit of FIG. 1;

FIG. 8 is a system configuration diagram showing one embodiment of a microprocessor including the clock pulse generation circuit of FIG. 1;

FIG. 9 is a board layout diagram showing one embodiment of the microprocessor of FIG. 8;

FIG. 10 is a connection diagram showing one embodiment for explaining a clock supply path of the microprocessor of FIG. 8;

FIG. 11 is a block diagram showing one embodiment of a clock controller included in the microprocessor of FIG. 8;

FIG. 12 is a conceptual diagram showing one embodiment of an application example that requires switching of the processing speed of the microprocessor of FIG. 8;

FIG. 13 is a conceptual diagram showing an embodiment for explaining the effect of switching the processing speed of the microprocessor of FIG. 8;

FIG. 14 is a partial configuration diagram showing one embodiment of a data transmission path of the microprocessor of FIG. 8;

FIG. 15 is a partial configuration diagram showing one embodiment of a data transmission path from a high-speed module to a low-speed module of the microprocessor of FIG. 8;

16 is a signal waveform diagram representing an operation of the data transmission path of FIG.

17 is a partial configuration diagram showing one embodiment of a data transmission path from a low-speed module to a high-speed module of the microprocessor of FIG. 8;

18 is a signal waveform diagram representing an operation of the data transmission path of FIG.

FIG. 19 is an operation flowchart showing an example of a clock pulse generation circuit included in the microprocessor.

[Explanation of symbols]

CPG clock pulse generation circuit, XOSC oscillation circuit, PLL PLL (phase locked loop) circuit, D
IV1 to DIV2: divider circuit, MUX1 to MUX4
... Multiplexer. G30-G31 ... Nand (NAN
D) Gates, Q31-Q32, Q41-Q42 ... P-channel MOSFETs, Q30, Q33-Q34, Q4
3. N-channel MOSFET. ST1 to ST7, S
T11 to ST17: Operation steps. CPU: central processing unit, ALU: arithmetic unit, MULT: multiplier
MMU: Memory management unit, TLB: Address conversion table, CACHE (Cache): Cache memory, BSC: Bus controller, REFC: Refresh controller, DMAC: Direct memory access controller, TIM (Timer): Timer Circuit, SCI: Serial communication interface, D / A (D / A converter)
…… Digital / analog conversion circuit, A / D (A / D
converter) ... Analog / digital conversion circuit, INTC ... Interrupt controller, RTC ... Real time clock circuit, CKC ... Clock controller, EXIF ... External interface, S-BUS ...
... System bus, C-BUS ... Cache bus, P-
BUS: peripheral bus, E-BUS: external bus. SUB
…… Semiconductor substrate. Driver: Clock driver, C
S1 to CS12 Clock switch. CTL: Clock controller control circuit, CPG-Reg, CS-R
eg ... register. PDA …… portable information terminal, LCD…
... Liquid crystal display. IREG: Input register, UL
T: unit latch circuit, CV1: clocked inverter. OREG: output register, MCKC: multi-clock controller. R1 to R2: resistance, C: capacitor, OG1 to OG3: OR gate, AG1 to AG
11 AND gate, V1 to V5 inverter.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Mitsugu Yamamoto 5--20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Shinichi Yoshioka 5 Kamimizuhoncho, Kodaira-shi, Tokyo No. 20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Susumu Narita 5--20-1, Kamisumi Honcho, Kodaira City, Tokyo Incorporated Hitachi, Ltd. Semiconductor Division (72) Inventor Ikuya Kawasaki Tokyo 5-20-1, Josuihoncho, Kodaira-shi, Semiconductor Division, Hitachi, Ltd. (72) Inventor Susumu Susumu 5-20-1, Josuihoncho, Kodaira-shi, Tokyo, Semiconductor Division, Hitachi Ltd. (72) Inventor Kiyoshi Hasegawa 5-20-1, Josuihoncho, Kodaira-shi, Tokyo F-ter, Hitachi RLS Engineering Co., Ltd. 5B033 AA01 BC01 5B062 AA05 HH02 HH07 5B079 BA01 DD04 DD20

Claims (16)

[Claims] A first internal circuit that receives a first clock signal and operates according to the first clock signal; and receives a second clock signal that is activated according to an activation signal and has a predetermined frequency, and receives the second clock signal having a predetermined frequency. A clock generation circuit which takes a time from the start of forming a third clock signal having a higher frequency and the start up to forming the third clock signal having the higher frequency; and A switching circuit for selectively supplying a third clock signal or a fourth clock signal having a lower frequency than the third clock signal to the first internal circuit as the first clock signal; When the fourth clock signal is supplied to the first internal circuit as the first clock signal, the clock generation circuit generates the fourth clock signal. A microprocessor for supplying a dynamic signal, and thereafter outputting the switching signal for switching the fourth clock signal to the third clock signal. 2. The clock controller according to claim 2, wherein
Before switching from the third clock signal to the third clock signal, a signal for inhibiting the fourth clock signal from being output as the first clock signal is supplied to the switching circuit. The microprocessor of claim 1, wherein: 3. The microprocessor according to claim 1, wherein the frequency of the fourth clock signal is lower than the frequency of the second clock signal. 4. The microprocessor according to claim 3, wherein said microprocessor includes a frequency dividing circuit for dividing said second clock signal to form said fourth clock signal. . 5. The clock generating circuit according to claim 1, wherein said clock generating circuit includes a phase locked loop circuit.
5. The microprocessor according to claim 2, 3 or 4. 6. The first internal circuit includes a central processing unit receiving the first clock signal as a first system clock signal and operating according to the first system clock signal. Term 1,
The microprocessor according to claim 2, 3, 4, or 5. 7. The clock controller selectively forms the switching signal and the start signal in accordance with a control register in which control data is set by the central processing unit and contents of the control data set in the control register. 7. The microprocessor according to claim 1, further comprising a control circuit. 8. The central processing unit, when the third clock signal is supplied as the first system clock signal, the fourth clock signal is supplied as the first system clock signal. 8. The microprocessor according to claim 1, wherein the microprocessor operates at a higher speed than when the microprocessor is in operation. 9. A first internal circuit that operates in response to a first system clock signal and selectively operates in a low-speed mode or a high-speed mode by switching the frequency of the first system clock signal; Circuit for forming a third clock signal having a higher second frequency based on a second clock signal having a higher frequency than the second clock signal, and a time period from when the circuit is started to when its output frequency is stabilized. And selecting the second clock signal or the divided signal thereof in the low-speed mode or until the output frequency of the clock generation circuit is stabilized after the clock generation circuit is started. A multiplexer for selecting the third clock signal and transmitting the selected signal to the first internal circuit as the first system clock signal. Microprocessor characterized. 10. The microprocessor according to claim 9, wherein said clock generation circuit includes a PLL circuit. 11. The switching from the selection of the second clock signal to the selection of the third clock signal by the multiplexer stops the supply of the first system clock signal to the first internal circuit. 11. The microprocessor according to claim 9, wherein the processing is performed after a period. 12. The first internal circuit includes a plurality of first modules that operate according to the first system clock signal, and the microprocessor includes:
A second internal circuit including a plurality of second modules that receive the second clock signal or a frequency-divided signal thereof as a second system clock signal and operate according to the second system clock signal; The first module includes a central processing unit, a multiplier and a memory management unit, and the second module includes a bus controller and a peripheral device controller. The microprocessor of claim 11. 13. The microprocessor according to claim 1, wherein the microprocessor selectively supplies the first system clock signal to each of the plurality of first modules, and supplies the first selection circuit to each of the plurality of second modules. And a second selection circuit for selectively supplying the second system clock signal.
0. The microprocessor according to claim 11 or claim 12. 14. The microprocessor according to claim 1, wherein the microprocessor is configured to:
And a static type latch for performing data transfer between the second module and the second module.
14. The microprocessor according to claim 12 or claim 13. 15. The clock generation circuit is selectively activated in response to occurrence of an event requiring high-speed processing in the high-speed mode, and the first internal circuit performs high-speed processing issued after the occurrence of the event. The high-speed mode is selectively set in response to a start request.
15. The microprocessor according to claim 13 or claim 14. 16. The microprocessor according to claim 1, wherein the microprocessor is provided for a portable information terminal having an input pen, and receives an event that requires high-speed processing in the high-speed mode in response to the start of writing of characters by the input pen. And recognizing the request for starting the high-speed processing in response to the end of writing of the character by the input pen.
A microprocessor according to claim 13, claim 14, claim 14, or claim 15.