KR890003482B1 - Clock interface circuits of personal computer - Google Patents

Abstract

This interfacing circuit supplies a low speed clock (477 MHz) and a high speed clock (8 MHz) according to the user's choice and improves the processing speed of system without modification of software. The clock interface circuit is composed of a first clock generation part (10) (high speed clock) and a second clock generation part (20) (low speed clock). A reset circuit (30) supplies the initial reset signal to the circuits (10,20). The selection part of clock input (40) supplies the selected clock out of two clock signals to the CPU.

Description

Personal computer clock interface circuit

1 is a clock generation driving chip circuit diagram.

2 is a block diagram according to the present invention.

3 is a detailed circuit diagram of FIG. 1 in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

10: first clock generator 20: second clock generator

30: reset circuit 40: clock input selector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply interface circuit of a personal computer. In particular, a low speed clock (4.77 MHz) and a high speed clock (8 MHz) can be supplied according to a selection, and the processing speed of the system can be improved without software modification. Relates to a clock interface circuit. Generally, microprocessors vary depending on the manufacturer, but there are two cases in which a clock generator is embedded in the processor and a clock generation driver chip is used. However, in the case of the ease of designing the electronic embedded system and the low speed low-end system, the latter case is frequently used in the high-speed high-end system, and the oscillation clock can be supplied according to the selection. In order to improve the performance, the clock generation driver chip is mainly used.

1 is an internal circuit of a clock generation driver chip for supplying a clock from the outside. The crystal oscillation circuit (X-TAL), the AND gate (AN10-AN20), the OR gate (OR10), the divider (DV10-DV20) , The part consisting of inverters B10 and B40 is the clock generation circuit 1, the part consisting of the Schmitt trigger ST and the deflip-flop DF30 is the reset circuit 2, and the AND gates AN30-AN50. The ready control circuit 3 is composed of the OR gates OR20 and OR30, the flip-flops DF10 and DF20, and the inverters B50 and B60. Therefore, the clock generation driver chip shown in FIG. 1 outputs a clock, reset signal, and ready signal to the CPU. The "low" signal is applied to the FC terminal (freuency / crystal select). Is applied to the divider DV10, and the signal generated from the crystal oscillation circuit X-TAL is divided in the divider DV10 so that the ratio of the "low" pulse width and the "high" pulse width is 2: 1. It is converted to a clock CLK and output to the CPU. In this case, when the "high" signal is applied to the F / C terminal, the above process is performed using the external signal as the reference signal through the EFI terminal (External Frequency). OSC (Oscillator) and PCLK (Peripheral Clock) are the general purpose clocks for peripheral integrated circuit, and CSYNC (Ciock Synchronization) input is for synchronizing with other clock generation circuits. "High" (synchronous preset). The third divider DV10 and the second divider DV20 start counting from the rising of the division clock after the CSYNC is "low" so that the CSYNC can keep at least two cycles of the division clock "high." The reset circuit 2 is composed of a schmitt trigger circuit ST and a deflip flop DF30. When a reset signal is generated, the schmitt trigger circuit ST removes noise due to hysteresis characteristics and the deflip flop DF30. ) Synchronizes the output of the Schmitt trigger ST to the clock generated by the clock generation circuit 1 and outputs the result to the reset circuit of the CPU.

The ready control circuit 3 is composed of an AND gate (AN30-AN50), an OR gate (OR20-OR30), inverters (B50, B60), and a flip-flop (DF10-DF20) to synchronize the ready signal with a clock drop. The signal is not available in normal ready. It is a signal that masks or enables RDY1 and RDY2 to AEN1 and AEN2, and inputs "High" after the required wait period for RDY1 and RDY2. The CSYNC terminal is used to select whether to synchronize with the first stage or the second stage. When RDY1 and RDY2 are synchronized to the clock and satisfy the set up time for the clock, synchronization is one stage and the CSYNC terminal is "high" or open. On the other hand, RDY1 and RDY2 are asynchronously inputted to the clock and when the set up time is not satisfied, two-stage synchronization is required and ASYNC is used as "low". The sampling timings of RDY1 and RDY2 become faster by 1/3 clock.

As described above, however, the internal oscillation circuit or the external clock is selected by the hardware, so there is no choice when the CPU is running. In other words, the F / C terminal of FIG. 1 is calibrated before the CPU or operation to ground ("low") or power supply ("high"). It was fixed to, so it could not be converted while it was running.

Accordingly, an object of the present invention is to provide a circuit capable of selectively supplying fixed low speed and high speed clocks to a CPU clock using two clock generation driving chips.

Another object of the present invention is to provide a system capable of improving the processing speed.

Another object of the present invention is to provide a low-cost system with high functionality because the existing software can be used as it is and the circuit is simply configured.

The present invention for achieving the above object is the first clock generator for making a high speed (8MHz) clock, the second clock generator for making a low speed (4.77MHz) clock, and the initial of the first and second clock generator A reset circuit for supplying a reset signal and a clock input selector for selectively inputting and generating the generated clocks of the first and second clock generators by a user's selection switch.

2 is a block diagram according to the present invention, the first clock generator 10 fixed to make a high-speed clock, the second clock generator 20 fixed to make a low-speed clock, and the first, second The reset circuit 30 for supplying the initial reset signal to the clock generators 10 and 20 and the generation clocks of the first and second clock generators 10 and 20 can be selectively input and supplied according to user selection. Consisting of a clock input selector 40.

Therefore, when the embodiment of the present invention is described by the above-described configuration, an 8 MHz high speed clock is generated in the first clock generator 10, a 4.77 MHz low speed clock is generated in the first clock generator 20, and a reset circuit is generated. After the initial reset signal is applied to the first and second clock generators 10 and 20 by 30, if the normal state is reached, one of the low and high speed clock signals input from the clock input converter 40 is selected by the user. Selected by and supplied to the CPU clock.

FIG. 3 is a detailed circuit diagram of FIG. 2 according to the present invention. The CSYNC, F / C, ASYNC, and RDY2 stages of the clock generation driver chip ICI are connected to ground, and a clock generator for generating 24 MHz is provided at the X1 and X2 stages. TAL1) and an adjustable variable capacitor (C1) connected in series and connected to ground through resistors R1 and R2 at each end correspond to the first clock generator 10, and the clock generation driver chip ( Connect the CSYNC, F / C, ASYNC, and RDY2 stages of IC2) to ground, and connect the 14.318MHz clock generator (X-TAL2) and the adjustable variable capacitor (C2) in series to the X1 and X2 stages. A part connected and connected to the ground through R3 and R4 corresponds to the second clock generator 20, and includes a reset switch SW2, a resistor R5, a capacitor C3, a diode D1, and a Schmitt trigger inverter. The part constituted by (ST1, ST2) corresponds to the reset circuit 30, and is configured to be input to the control terminal through the selection switch SW1 and the inversion gate N1 to the 30 state buffer OBL. Minutes corresponds to a clock input selector 40.

Therefore, when a specific embodiment of the present invention is described in detail, since the CSYNC, F / C ASYNC, RDY2, and GND terminals of the clock generation driving chips IC1 and IC2 are fixed to the ground terminal, the inputs of X1 and X2 can be accepted. It is not enabled. At this time, 24MHz and 14.318MHz generated from the clock generators X-TAL1 and X-TAL2 are respectively input to the clock generation driver chips IC1 and IC2 through the X1 and X2 stages, respectively. 8 MHz is output to the clock terminal CLK of the IC1, and 4.77 MHz is output to the clock terminal CLK of the second clock generation driver chip IC2. In addition, the standby signal READY and the reset signal of the CPU are output from the clock generation driver chips IC1 and IC2 and input to the 3-state buffer OBL. At this time, one of the two input ports of the 3-state buffer OBL is activated according to the operation of the CPU clock selection switch SW1, so that the 3-state buffer OBL is the first clock generation driving chip IC1 or the second clock. The clock CLK, the reset RDSET, and the READY signal can be supplied to the CPU generated by the generation driver chip IC2. On the other hand, the reset switch SW2 allows the clock generation drive chips IC1 and IC2 to be reset at the time of power-on reset and initialization, and the entire system can be reset. The duty cycle control circuit (DYZ) adjusts the duty cycle required in the direct memory access (DNA), which receives and adjusts the 4.77MHz signal generated by the clock generation driver chip ic2.

As described above, the conventionally designed CPU can be easily selected when using a high-grade CPU and can increase the processing speed and can be used without software modification. have.

Claims (1)

In the CPU clock supply interface circuit, a first clock generator 10 for generating a high speed clock, a second clock generator 20 for generating a low speed clock, and the first and second clock generators 10 and 20 A reset circuit 30 for supplying an initial reset signal to the input signal, and an input for selecting a corresponding clock to a state of a clock selection switch among the generated clocks of the first and second clock generators 10 and 20 and outputting the same to the CPU. A clock interface circuit of a personal computer, comprising: a clock input selector;

Images