JP2658889B2 - Semiconductor integrated circuit and test method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a test method therefor, and more particularly to a semiconductor integrated circuit in which an internal clock operates by dividing an input clock and a test method therefor.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as "LSI")
In many cases, the internal circuit operates in synchronization with a clock. Recently, the operating clock frequency of LSI has been greatly improved with the progress of technology.

For this reason, the frequency of an LSI tester used in a test at the time of manufacturing an LSI cannot be improved, and the LSI tester and the LSI have almost the same maximum operating frequency.

In an LSI such as a microprocessor or a microcontroller, a duty cycle of 50%, that is, a clock in which the high potential width and the low potential width of the internal operation clock match each other, is usually used as the internal operation clock. In many cases, the frequency is divided by 1/2.

In this case, if the internal operating clock frequency of the LSI is substantially equal to the maximum operating frequency of the LSI tester, L
It can be measured with SI tester. In other words, a signal at twice the rate of the fundamental wave is given from the LSI tester as an input clock of the LSI under test, and is the actual measurement target.
It is assumed that the input and output signals of the LSI are performed with the fundamental wave of the LSI tester. As a result, measurement can be performed even when the internal operation of the LSI approaches the maximum operating frequency of the LSI tester.

FIG. 5 is a block diagram (referred to as "conventional example 1") showing a clock supply circuit of a microprocessor in which an input clock is divided and an internal circuit operates.

In FIG. 5, a microprocessor 201
Are the clock input (CLKIN) 202 and the reset input (RESE)
T) 203, test input (TEST) 204, and clock output (C
LKOUT) 205. The microprocessor 201 includes a central processing unit (hereinafter, referred to as a “CPU”).
206, a clock frequency divider 207, and a pull-up resistor 208.

FIG. 6 shows the details and operation timing of the clock frequency divider 207. As shown in FIG. 6 (A), the clock frequency division is realized by 1/2 of the edge trigger by using the flip-flop 301 which is synchronized with the rising edge. That is, as shown in the timing chart of FIG. 6B, the output changes in synchronization with the rising of the input.

In FIG. 5, a clock input (CLKIN) 202
The clock signal input from the
The frequency is divided by two and the duty is assumed to be 50%. The clock is supplied to the clock input terminal (CPUCLK) of the CPU 206, and is further output from the clock output (CLKOUT) 205 to the outside. The clock signal output from the clock output (CLKOUT) 205 is used by a peripheral function circuit (not shown) other than the microprocessor 201.

The reset signal input from the reset input (RESET) 203 is input to the CPU 206, but this reset signal is not used for the clock frequency divider 207. That is, the clock frequency divider 207 outputs the reset input (RESET) 203
It is not reset by the reset signal input from.

One reason for this is that the reset input (RESET) 2
Even during the period in which the reset signal input to the input terminal 03 is active, the microprocessor 201 needs to continuously supply the clock signal from the clock output (CLKOUT) 205 to an external peripheral circuit (not shown). That is because Another reason is that it is necessary to supply a clock to the CPU 206 in order to reset a synchronous circuit (not shown) inside the CPU 206.

A signal input from a test input (TEST) 204 is a control signal for testing the CPU 206 and is shown in FIG.
As shown in the figure, the test mode control terminal of CPU206 (TEST)
And is used substantially only during testing during LSI manufacturing.

[0013] A general user can use the microprocessor 20.
When 1 is used (that is, during normal operation), the test input (TEST) 204 is fixed to “1”, or is not connected, and the pull-up resistor 208
The high potential is supplied to a test mode control terminal (TEST) of the CPU 206, and the CPU 206 performs a normal operation.

At the time of testing at the time of manufacturing an LSI or the like, the test input (TEST) 204 is set to "0" to activate a test function provided in the CPU 206.

In the timing chart of FIG.
The output (i) is the output when the value of the flip-flop 301 (= output Q) is “1” at the time of power-on, and the output (ii) is the flip-flop when the value of the flip-flop 301 is “0” at the power-on. The signal waveform of the output of the loop 301 is shown.

As shown in FIG. 6B, the phase of the clock supplied to the CPU 206 at a predetermined time T differs depending on the state of the flip-flop 301 in the clock frequency divider 207 at the time when the power is turned on.

[0017]

In a test at the time of manufacturing an LSI or the like, a signal is input from an LSI tester to an LSI which is a device under test at a certain time, and an output signal from the LSI is output at each time to an expected value. The comparison is used to determine whether the LSI is good.

As described with reference to FIG. 5, in the conventional microprocessor, the clock divider 207 does not have a phase synchronization function.

For this reason, in a test of a microprocessor having a clock frequency divider having a configuration as in the conventional example 1 of FIG. 5, a signal which is first output from the LSI is checked from the start of clock supply after power is turned on. It is necessary to perform phase matching with the expected value based on That is, the LSI tester needs to perform start-stop synchronization based on an appropriate output signal of the microprocessor as the device under test.

When such start-stop synchronization is performed, specific know-how is required for selecting a signal to be a reference for start-stop synchronization and describing a control program of an LSI tester.

Further, an extra time is required for an LSI test time because a method of adding an item for outputting a signal for performing start-stop synchronization before an item originally intended to be tested is employed.

With the development of high integration and high functionality of LSIs, test development and test time of the LSIs occupy a large proportion of the manufacturing cost of the LSIs. This is a factor that hinders a reduction in LSI manufacturing costs.

Next, with reference to FIG. 7, a description will be given of a technique disclosed in Japanese Patent Application Laid-Open No. Sho 64-47975 (hereinafter referred to as "Conventional Example 2") as a configuration of a conventional LSI having a test mode. Conventional example 2 employs a flip-flop in an integrated circuit that can set a normal input signal in a combination that is impossible in an actual use state, and combines an output of the flip-flop with an input that does not affect a part to be tested. A configuration has been proposed in which a part or all of a test target portion is set to a test state or a reset state.

In FIG. 7, A is an input terminal of a basic clock to the frequency dividing circuit 1, and terminals B, C, D and E are input terminals which do not affect the test of the functional block 4, and terminals B and D , E are connected to one input of AND gates 8, 3, and 7, the other input of these AND gates is connected to the output of D-type flip-flop 9, and the output of AND gate 8 is Connected to reset input. Terminal F is a reset input terminal, terminals G and H are AND gate 1
Although 0 is input, it does not become “1” at the same time in the actual use state. The output of the functional block 4 which is the main test target is input to the non-test target functional block 5, and further connected to the input of the multiplexer 6 together with the output of the functional block 5, and the select input of the multiplexer 6 is connected to the AND gate 7. .

In Conventional Example 2, in the test state, a normal input signal which does not affect the test target block is used for controlling the test target block. This controls a multiplexer that inputs a special clock to the test target block and observes a signal from the test target block to another block as an output signal directly.

As described above, in the conventional example 2, the flip-flop for distinguishing between the test state and the normal state is provided in the LSI, and is used for switching various input selectors and output multiplexers.

However, in the conventional example 2, since these selectors and multiplexers are inserted in the path of the normal signal, there is an adverse effect on the maximum operating frequency of the LSI. In particular, the insertion of a selector or a multiplexer in the clock supply signal path of the LSI is a recent technical trend described above (that is, a significant improvement in the operating frequency of the LSI).
There is a problem from the point of view.

In the second conventional example, since the flip-flop indicating the test state is set when the combination of the normal signals is not normally used, the general user erroneously sets the test state in the actual use. There is a danger that

In particular, when the behavior of a signal that does not hinder normal operation, such as slight overlap or noise when the external input signal changes, sets the flip-flop for test control, the conventional example 2 is used. A device using an LSI including the configuration described above causes a malfunction with poor reproducibility in the market.

Further, when the LSI to be tested cannot be divided into a plurality of blocks, there is no ordinary signal which does not affect the block to be tested which is a premise of applying the second conventional example.

Next, the prior art will be described based on Japanese Patent Publication No. 1-153986 (hereinafter referred to as "Conventional Example 3"). Conventional example 3
However, since the test generation circuit uses a dedicated terminal for test mode setting, a separate terminal other than the normal terminal is required, resulting in poor utilization efficiency. As a solution to the problem that a structure with a higher withstand voltage is required, a test signal generation circuit that sets the test mode of the logic integrated circuit using the normal terminal without using a dedicated terminal for test mode setting is provided. It is intended to provide.

In the third conventional example, a transition point at which the reset input signal, which is a normal input signal, changes to the inactive level is detected, and a pulse for a half clock synchronized with the input clock is generated. This pulse is converted to TDA
The transition to the test mode is performed by taking the logical product of the delayed signal and the original pulse.

Since the analog delay time is almost constant irrespective of the input clock, if the analog delay time is sufficiently longer than the operating frequency of the LSI, it is not possible to shift to the test mode during normal operation of the LSI. Absent.

When it is necessary to shift to the test mode during a test such as when manufacturing an LSI, the input clock cycle is changed to the analog delay time TD after the inactive change of the reset signal.
By setting the length sufficiently longer than A, the test mode transition signal is generated from the logical product output of the original pulse and the analog delay pulse.

However, in the conventional example 3, since the analog delay is used inside the LSI, the delay time TDA changes depending on the manufacturing conditions, the operating voltage, and the operating temperature at the time of manufacturing the LSI. That is, the minimum value and the maximum value of the delay time TDA have a large width.

Further, at the minimum value of the delay time TDA,
To avoid erroneous transition to the test mode during normal use, an analog delay circuit much larger than the minimum operating frequency expected during normal use by the user must be provided.

As an example, when a user uses an LSI having a maximum operating frequency of 20 MHz (megahertz) at a frequency of 5 MHz, it is much larger than a half clock of 5 MHz (= 200 nanosecond period), for example, about 5 milliseconds. Need to be provided.

However, providing a 5 ms delay circuit only for a test circuit under the recent high integration / high speed operation LSI process is a waste of valuable chip area.

In the third conventional example, the lower limit of the input clock must be specified in order to prevent an erroneous transition to the test mode during normal operation.

However, recently, when the LSI is a microprocessor or a microcontroller, it is required to lower the operating frequency to reduce the power consumption of the device. The prior art 3 cannot be applied to applications in which the power consumption of the device is reduced by gradually lowering the input clock frequency of the microprocessor while waiting for keyboard input or the like.

Therefore, the present invention solves the above-mentioned problems,
An object of the present invention is to provide a semiconductor integrated circuit provided with a clock frequency dividing circuit, which enables synchronization of clock phases and facilitates testing, and a test method thereof.

[0042]

According to the present invention, there is provided a semiconductor integrated circuit having a test mode, comprising: a test signal input unit, a test signal decode unit, a clock input unit, and a clock input unit. Frequency dividing means for dividing the clock inputted from the test signal input means, and using a result obtained by decoding the test signal inputted from the test signal input means by the test signal decoding means to the frequency dividing means. There is provided a semiconductor integrated circuit characterized by performing clock phase adjustment.

In the present invention, preferably, the period of the clock input to the clock input means is extended during the period in which the phase of the clock is adjusted by the test signal input from the test signal input means. It is a feature.

Further, according to the present invention, the test signal decoding means may output a clock signal to the frequency dividing means based on a combination of test signals input from the test signal input means even in a normal operation other than the test mode. Characterized in that a signal for performing the phase matching is supplied.

According to the present invention, a test of a semiconductor integrated circuit comprising test signal input means, test signal decode means, clock input means, and frequency dividing means for dividing a clock input from the clock input means is provided. A method for supplying a predetermined signal to the test signal input means, wherein the test signal decoding means decodes a signal input from the test signal input means to the frequency dividing means, and wherein the test signal decoding means And a method for testing a semiconductor integrated circuit, wherein the clock phase is adjusted based on the output of the semiconductor integrated circuit.

In the test method of the present invention, during a period in which the phase is adjusted by the test signal input from the test signal input means, the cycle of the clock input to the clock input means is extended to adjust the phase of the clock. It is characterized by:

[0047]

According to the semiconductor integrated circuit of the present invention, the phase of the clock output is fixed during the test mode operation regardless of the initial state of the flip-flop constituting the clock frequency dividing circuit. Therefore, the test of the LSI tester can be simplified by simplifying the program of the LSI tester at the time of manufacture, and the test time at the time of manufacture can be shortened. For this reason, the present invention achieves a reduction in the manufacturing cost of the semiconductor integrated circuit.

According to the present invention, the period of the clock input to the clock input means is extended during the period in which the clock phase is adjusted by the test signal input from the test signal input means. The setup time and the hold time for the clock input of the reset signal of the frequency divider are sufficiently ensured, and detailed adjustment of the timing and the like are not required, thereby facilitating the test.

Further, according to the present invention, the phase of the clock output signal from the clock frequency divider is always constant not only in the test mode but also in the normal operation.
In addition to facilitating test, design facilitation such as timing design is also achieved.

[0050]

Embodiments of the present invention will be described below with reference to the drawings.

[0051]

FIG. 1 is a block diagram showing a clock supply circuit of a microprocessor according to an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG.
The elements 1 to 208 perform the same functions as those described in the first conventional example, and therefore will not be described. Only the differences from the first conventional example will be described below.

In FIG. 1, a clock divider 101 with reset is provided instead of the clock divider 207 used in the conventional example 1 of FIG.

In the conventional example 1 shown in FIG. 5, a signal for controlling the test mode of the CPU 206 is a test input (TES
T) 204, a single test signal is input. However, in the present embodiment, as shown in FIG.
ST (1-0)) 102 receives two test signals.

Further, in this embodiment, the test input (TEST (1-
0)) A decoder 103 for decoding the test signal input from the input terminal 102 and OR gates 104 and 105 are provided.

FIG. 2 shows details and operation timing of the clock frequency divider 101 according to one embodiment of the present invention.

As shown in FIG. 2A, in the present embodiment, the clock frequency division is realized by half the frequency of the edge trigger using the rising synchronous flip-flop 401. The output changes in synchronization with the rising edge of the input as shown in the timing chart in FIG.

The flip-flop 401 has a reset input (R) asynchronous with the clock.

Next, the operation of the clock phase synchronization system according to the present invention will be described with reference to FIGS.

In this embodiment, similar to the conventional example 1 shown in FIG.
The clock signal input from the clock input (CLKIN) 202 is frequency-divided by ク ロ ッ ク in the clock divider 101, supplied to the clock input terminal (CPUCLK) of the CPU 206, and externally output from the clock output (CLKOUT) 205. Is output.

The two test signals input from the test input (TEST (1-0)) 102 are input to the decoder 103 and decoded.

The decoder 103 is a general two-input, four-output decoder. For example, the output becomes “1” corresponding to the combination of the input signals described in the decoder 103 in the figure. That is, when the signal input to the decoder 103 is “00”, O
When one input of the R gate 105 is “1” and is “01”,
Both the other input of the OR gate 105 and one input of the OR gate 104 are "1". When the input is "10", the other input of the OR gate 104 is "1".

A general user can use the microprocessor 201
Is used (that is, during normal operation), the test input (TEST (1-0)) 102 is fixed to “11” or used.
Alternatively, “11” is input to the decoder 103 by the pull-up resistor 208 by making no connection. In this case, CPU20
6 is in a normal operation state, and the reset signal 106 supplied to the reset input (R) of the clock frequency divider 101 is also in an inactive state.

The CPU 206 activates the test function by the OR gate 105 which outputs the logical sum of the "00" output and the "01" output of the decoder 103. In this embodiment, the test mode control terminal (TEST) of the CPU 206 is active when it is "1".

When the input of the decoder 103 is "10" or "0"
When 1 ”, the clock divider
A reset signal 106 for performing phase synchronization with the reset input (R) of 101 is supplied.

Therefore, the “01” output of the decoder 103 is
The test function of 6 is activated and the reset signal 106 is activated. When the input of the decoder 103 is “10”, C
PU 206 is set to a normal operation state.

In the timing chart of FIG. 2B, the output (i)
Is the value of the flip-flop 401 (= output
When Q) is "1", the output (ii) indicates a case where the value of the flip-flop 401 is "0" at the time of power-on.

As shown in FIG. 2B, the flip-flop 401 is reset by the phase synchronization reset signal 106 at the time TR irrespective of the value of the flip-flop 401 inside the clock frequency divider 101 at the time of turning on the power. At the subsequent time T, the phase of the clock supplied to the CPU 206 is always constant.

That is, as shown in FIG. 2B, the reset signal 106 input to the reset input (R) of the clock frequency divider 101 is counted after a predetermined clock count from the power-on time (see FIG. In B), for example, at the fourth clock), the potential is set to a high level.
Output (Q) is forced (asynchronous) even at high potential
(See the arrow of the output (ii) in FIG. 2B), and at time TR, both the outputs (i) and (ii) are reset to the low potential. After the time TR, the flip-flop 401 divides the frequency by し て in synchronization with the rising edge of the input, and the phases of the outputs of the clock frequency divider 101 match regardless of the initial state of the flip-flop 401 .

In this embodiment, the reset signal 106 for synchronizing the phase of the clock frequency divider 101 is supplied to the test input (TEST (1-
0)) Since it is activated when “10” or “01” is input to 102, the test input (TEST (1-0)) is used in both normal operation and when using the test function. Clock phase synchronization can be performed by setting the test signal input from 102.

[0070]

Embodiment 2 Hereinafter, another embodiment of the present invention will be described.

In an actual LSI test, an analog delay of a signal must be considered.

In particular, as in the above embodiment, the phase matching is generated from the decoded output signal of the decoder 103 which receives the test signal input to the test input (TEST (1-0)) 102. In this case, since the decoding delay is large, the test signal T is applied by the signal applied from the LSI tester side.
It is difficult to adjust the timing from changing EST (1) and TEST (0) until the actual phase adjustment is performed.

Then, in the flip-flop 401,
If the reset signal 106 for performing the phase adjustment cannot secure sufficient setup time and hold time for the clock input, a malfunction occurs.

The minimum period of the signal input from the LSI tester is about the maximum operating frequency of the microprocessor 201,
That is, since the frequency is often about the clock cycle input to the clock input (CLKIN) 202, the decoder 103
It is difficult to input the test input (TEST (1-0)) 102 and the clock input (CLKIN) 202 in consideration of the delay such as. This is a decoder 1 which is an internal circuit of the microprocessor 201.
This is also because the timing of the reset signal 106 output via the delay of the 03 and the OR gate 104 cannot be directly controlled by the LSI tester.

Therefore, in this embodiment, as shown in the operation timing chart of FIG. 2B, the clock input (CLKIN) 202 is performed during the phase adjustment by the reset signal 106.
The cycle of is extended.

As a result, with respect to the asynchronous reset signal 106 of the flip-flop 401, sufficient setup time and hold time for the clock input can be secured. Further, according to the present embodiment, the timing design for the test is facilitated.

[0077]

Embodiment 3 Next, a microprocessor according to the present invention will be described.
A test method using an LSI tester will be described. 3 and 4
Is an example of a sequence of test patterns (test vectors) applied from the LSI tester to the microprocessor 201 as the device under test when the microprocessor provided with the clock phase synchronization circuit described in the above embodiment is tested by the LSI tester. Timing diagram showing LSI
4 shows operation steps of the tester.

As shown in FIG. 3, the clock input (CLKI
N) A predetermined number N1 of clocks are supplied to 202 at a predetermined period m, and then the period of the half clock period is changed to M (where M is larger than m), and then the original clock is returned again. A clock signal is supplied for a predetermined number N2 times at a period m.

TEST among test inputs (TEST (1-0)) 102
A pattern in which (1) is set to a high potential at the timing of the illustrated time TR is prepared. The test input 102 is set so that a low potential state is applied to TEST (0). A reset input (RESET) 203 is a signal for resetting the CPU 206. As shown in FIG. 3, after a predetermined number (N1) of clocks are supplied by the LSI tester, for example, “10” or the like is set as the test input (TEST (1-0)) 102 in order to This is for resetting the clock frequency divider 101 after supplying a predetermined number of times.

As shown in FIG. 3, according to the present embodiment, since the semiconductor integrated circuit as the device under test includes the clock phase synchronization circuit, the clock phase synchronization circuit is provided at a predetermined timing from the LSI tester side. A test signal for resetting may be supplied. As described above, according to this embodiment, the LSI tester does not need to perform start-stop synchronization with the LSI under test, so that the test pattern is shortened,
In addition, the control program is simplified.

FIG. 4 shows a case where the LSI tester tests the microprocessor 201 as the device under test.
4 is a flowchart illustrating a typical example of an operation sequence for generating the clock input (CLKIN) 202 of FIG.

As shown in FIG. 4, first, for a clock input pin, an input signal waveform including a clock cycle, a timing, a waveform format, and a use pattern is defined (step 501).

Microprocessor as device under test
The clock signal (CLKIN) 202 of 201 is supplied with a clock signal for a predetermined number N1 times at a predetermined period m set in step 501.
The voltage is applied from the LSI tester (step 502). Next, the period of the half clock period is changed to M and the clock input (CLKIN) 2
A signal is applied to 02 (step 503). The change of the clock cycle is performed, for example, by switching a timing set for defining a test cycle and the like provided in an ordinary LSI tester. Thereafter, a predetermined number N2 of clock signals are output to the clock input (CLKIN) 202 again at the predetermined period m (step 504).

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principle of the present invention. For example, in the above-described embodiment, the present invention has been described by taking the microprocessor having the clock divider as an example, but the present invention includes other integrated circuits.

[0085]

As described above, according to the semiconductor integrated circuit provided with the clock phase synchronization circuit according to the present invention,
This facilitates testing, such as simplifying the program of the LSI tester at the time of manufacturing, and can shorten the testing time at the time of manufacturing as compared with the related art, thereby achieving a reduction in manufacturing cost.

According to the present invention, the period of the clock input to the clock input means is extended during the period in which the phase of the clock is adjusted by the test signal input from the test signal input means. At times,
The setup time and the hold time for the clock input of the reset signal of the clock frequency dividing circuit are sufficiently ensured, and detailed adjustment of timing and the like are not required, thereby facilitating the test.

According to the semiconductor integrated circuit of the present invention,
In the reset operation after power-on, not only in the test mode but also in the normal operation, the phase of the clock output signal from the clock frequency divider is always constant, thereby facilitating the test. In addition, the design of circuits has been simplified, such as timing design.

Further, according to the method of testing a semiconductor integrated circuit provided with a clock phase synchronization circuit according to the present invention, test simplicity can be achieved by simplifying a program of an LSI tester at the time of manufacture, and a test at the time of manufacture can be achieved. Since the time can be shortened as compared with the conventional case, the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a clock supply circuit of a microprocessor according to an embodiment of the present invention.

FIG. 2A is a detailed explanatory diagram of a clock frequency divider according to one embodiment of the present invention. 6B is a timing chart illustrating an operation sequence of the clock phase synchronization circuit.

FIG. 3 is a timing chart according to the test method of the present invention.

FIG. 4 is a flowchart showing control of a test program of an LSI tester according to the test method of the present invention.

FIG. 5 is a block diagram showing a clock supply circuit of a microprocessor according to the related art.

FIG. 6A is a detailed explanatory diagram of a clock frequency divider according to a conventional technique. 6B is a timing chart of a clock.

FIG. 7 is a block diagram showing a configuration of a test method according to Conventional Example 2.

[Explanation of symbols]

 101 Clock divider 102 Test input 103 Decoder 105, 104 OR gate 106 Reset signal 201 Microprocessor 202 Clock input 203 Reset input 205 Clock output 206 Central processing unit (CPU) 207 Clock divider 208 Pull-up resistor

──────────────────────────────────────────────────続 き Continuation of front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 27/04 (56) References JP-A-56-14353 (JP, A) JP-A-56-56 140447 (JP, A) JP-A-5-12461 (JP, A) JP-A-5-243933 (JP, A) JP-A-61-94131 (JP, A) JP-A-3-92914 (JP, A) JP-A-5-281298 (JP, A) JP-A-4-363711 (JP, A) JP-A-5-20113 (JP, A) JP-A-58-144763 (JP, A) JP-A-6-118139 (JP, A) JP-A-7-307650 (JP, A)

Claims (3)

(57) [Claims] 1. A test signal input means and a test signal input from the test signal input means.
A semiconductor integrated circuit having a test mode , comprising: test signal decoding means for coding; clock input means; and frequency dividing means for dividing a clock input from the clock input means.
Oite, results a test signal inputted from said test signal input means is decoded by said test signal decoding means the division
Before the clock phase is adjusted by the means,
The period of the clock input to the clock input means is extended.
A semiconductor integrated circuit, wherein the phase of the clock is adjusted in the set state . 2. The test signal decoding means according to claim 1 , wherein:
Test signal input means
Based on the normal operation other than the test mode,
To adjust the clock phase to the frequency dividing means
Supplying a signal of
The semiconductor integrated circuit according to claim 1. 3. A test signal input means, and a test signal input from the test signal input means.
Test signal decoding means for coding, clock input means, and frequency division of a clock input from the clock input means.
That the frequency dividing means comprises a semiconductor integrated circuit having a test mode, test
When performing a test using a test device, the test signal of the semiconductor integrated circuit is transmitted from the test device.
Test of a predetermined logical value for the signal input means
A test signal in the semiconductor integrated circuit.
The test signal input from the test signal input means.
Based on the output decoded by the
During the period in which the frequency dividing means performs clock phase adjustment ,
The clock input of the semiconductor integrated circuit from a test device
The period of the clock supplied to the means is extended,
A method for testing a semiconductor integrated circuit, comprising: