JP2002330062A - Warming-up detecting circuit, power on reset circuit and starting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the reset period of a logic circuit always constant, and to make the reset period necessarily longer than a warming-up period regardless of the rising time of a power source. SOLUTION: An oscillating clock is transmitted through an oscillation stabilizing circuit so that fluctuation at the time of power supply can be removed, and that a stable clock can be obtained. This stable clock is directly counted by a counter, and when the counted value reaches a prescribed value, the output signal is inverted, and a warming-up period is ended. At the same time, the stable clock is boosted, and when the boosted value reaches a prescribed value, the output of an inverter which inputs this is inserted, and a reset period is ended. Thus, it is possible to set the warming-up period and the reset period as a prescribed period regardless of the rising time of a power supply voltage. Also, it is possible to always hold this relation by setting the reset period longer than the warming-up period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a warm-up detection circuit which is mounted on an LSI or the like and sets a warm-up period from the start of clock oscillation to the start of the circuit, and resets the circuit when power is turned on, and then releases the reset. The present invention relates to a power-on reset circuit and a start-up circuit in which a warm-up circuit and a power-on reset circuit are integrated.

[0002]

2. Description of the Related Art In an LSI or the like, when a power supply is turned on, a warm-up detection circuit for setting a warm-up period until a logic circuit operates stably is provided. A power-on reset circuit is provided to make the operable state.

FIG. 9 is a block diagram showing a configuration example of a conventional warm-up detection circuit. A clock 100 generated by a clock oscillation circuit (not shown) is
, And outputs a frequency-divided signal 101 to the counter 2. The counter 2 counts the frequency-divided signal 101, and when reaching a predetermined value, outputs a warm-up signal 103 indicating that the warm-up period has ended to a logic circuit (not shown). The warm-up period secures a time until the waveform is stabilized after the oscillation of the clock 100 starts.

FIG. 10 is a circuit diagram showing a configuration example of a conventional power-on reset circuit. The drain side of the P-type MOS transistor (P-Tr) 3 is grounded (VSS level) via the capacitor C1, and a reset signal 200 is output from the terminal of the capacitor C1 through the inverters 4 and 5.

When the power supply VDD is turned on, the reset signal 200
Is at a low level, and a logic circuit (not shown) is in a reset state. Thereafter, a current is supplied to the capacitor C1 through the transistor 3, and the terminal voltage D increases. When the terminal voltage D exceeds a predetermined voltage, the inverter 4 is inverted, the output thereof becomes low level, and the output of the inverter 5 becomes high level. . Thus, when the reset signal 200 becomes high level, the reset of the logic circuit (not shown) is released, and the logic circuit becomes operable.

[0006]

FIG. 11 is a timing chart for explaining the operation of the above-described conventional power-on reset circuit and the conventional warm-up detection circuit when the power supply rises slowly. FIG. 11A shows the power supply voltage V
It shows a change with time of DD, and it takes time from turning on the power supply to a predetermined voltage. FIG. 11B shows an oscillation waveform of the clock 100. The warm-up detection circuit determines the warm-up period 60 by dividing the frequency of the clock immediately after the start of oscillation by the divider 1 and counting the frequency. In this case, it takes several milliseconds until the internal operation starts, and if the oscillation frequency fluctuates until the internal operation is stabilized, the warming-up period 60
Fluctuates, an error occurs in the warm-up period 60.

FIG. 11C shows the change over time of the terminal voltage of the capacitor C1 of the power-on reset circuit of FIG. When the power supply voltage VDD rises and the terminal voltage D of the capacitor C1 also rises and reaches the predetermined value VIH, the inverters 4 and 5 are inverted, and the reset signal 200 goes low as shown in FIG. (VSS level)
To a high level (VDD level), and the reset of a logic circuit (not shown) is released.

However, when the power supply rises slowly as in the case of FIG. 11, the reset period 50 of the logic circuit is shortened, so that the reset is released during the warm-up period 60 and the logic circuit operates with a fluctuating clock. There is a problem that it may cause a malfunction.

Here, if the rise of the power supply is slow, the operation start time of the inverters 4 and 5 is delayed.
The reset signal 200, which is the output of the inverter 5, is undefined, and the logic circuit is not in a reset state. After that, when the power supply rises to some extent and the inverters 4 and 5 are in the operating state, the reset signal 200 becomes low level and the logic circuit is in the reset state.
Since the terminal voltage D of the capacitor C1 has risen considerably and reaches VIH immediately and the reset period 50 is immediately released, the reset period 50 is shortened. In an extreme case, the reset period may be lost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. It is an object of the present invention to always keep a reset period of a logic circuit constant regardless of a rise time of a power supply and to make a warm-up period always. A power-on reset circuit that can make the reset period longer than the power-on reset circuit, a warm-up detection circuit that removes fluctuations from the clock waveform during the warm-up period, and can set a high-precision warm-up period, To provide a start-up circuit provided.

[0011]

Means for Solving the Problems To achieve the above object, a first means for solving the problems is as follows: a first reference voltage;
Oscillation stabilization that has a second reference voltage and generates a rectangular-wave stabilized clock synchronized with the input clock when the input clock is input across the first and second reference voltages. And a counter that counts the stabilizing clock generated by the oscillation stabilizing circuit and inverts the output signal when the count value reaches a predetermined value.

The second means has a first reference voltage and a second reference voltage, and the input clock is the first and second clocks.
When the state is input across the reference voltage, an oscillation stabilization circuit that generates a rectangular wave-shaped stabilization clock synchronized with the input clock, and a stabilization clock generated by the oscillation stabilization circuit, The booster includes a booster circuit for sequentially boosting an output voltage for every third reference voltage in synchronization with a cycle of an input clock, and at least one or more inverters for inputting an output voltage of the booster circuit.

The third means has a first reference voltage and a second reference voltage, and the input clock is the first and second clocks.
When a state is input across the reference voltage, an oscillation stabilization circuit that generates a rectangular wave-shaped stabilization clock synchronized with the input clock, and counts the stabilization clocks generated by the oscillation stabilization circuit, When the count value reaches a predetermined value, a counter for inverting the output signal and a stabilizing clock generated by the oscillation stabilizing circuit are input, and the output voltage is synchronized with the cycle of the input clock by a third reference voltage. A step-up circuit for sequentially boosting the voltage every minute, and at least one or more inverters for inputting an output voltage of the step-up circuit in an integrated circuit; A warm-up period of a logic circuit in the integrated circuit is set, and a reset period of the logic circuit in the integrated circuit is set by a change in polarity of an output signal of the inverter. To set.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a warm-up detection circuit according to an embodiment of the present invention. The warm-up detection circuit divides the power supply voltage VDD to generate reference voltages V1 and V2, thereby generating voltage dividing resistors R1 and R2.
R2, R3, an operational amplifier 11 for comparing the reference voltage V2 with the clock 100, an operational amplifier 12 for comparing the reference voltage V1 with the clock 100, an inverter 13 for inverting the output of the operational amplifier 12, and an output of the operational amplifier 11 and the inverter 13. An oscillation stabilizing circuit 15 having a flip-flop 14 for inputting and generating a stable clock 104;
The clock 10 generated by the oscillation stabilizing circuit 15
It has a counter 16 that counts 4 and generates a warm-up signal 103 when it reaches a predetermined value.
The terminal A of the flip-flop 14 is a reset terminal,
Terminal B is a set terminal, and C is an output terminal. The flip-flop 14 is composed of NOR circuits 141 and 142 and an inverter 143.

Next, the operation of this embodiment will be described.
A clock 100 generated by a clock oscillation circuit (not shown) has a waveform as shown in FIG. 2A and is input to the non-inverting terminals (-) of the operational amplifiers 11 and 12.
On the other hand, the power supply voltage VDD is divided by a series circuit of resistors R1, R2, and R3, and a reference voltage V2 is input to the inverting terminal (+) of the operational amplifier 11 from a connection point of the resistors R1 and R2, and the resistors R2 and R3 The reference voltage V1 is input to the inverting terminal (+) of the operational amplifier 12 from the connection point.

Here, it is assumed that the clock 100 is in the rising direction between V1 and V2. At this time, the operational amplifier 11 is at a low level (“0”), and the operational amplifier 12 is at a high level (“1”) and is input to the terminal A of the flip-flop 14. The output of the operational amplifier 12 is inverted by the inverter 13 and input to the terminal B of the flip-flop 14. At this time, as shown in the truth table of FIG. 3, "0" and "0" are input to the terminals A and B of the flip-flop 14, and the output of the terminal C of the flip-flop 14 is "0".

Thereafter, the value of the clock 100 rises and V
When the number becomes 2 or more, the output of the operational amplifier 11 becomes high level, so that the terminals A and B of the flip-flop 14 become "1" and "0" as shown in the truth table of FIG. Is changed from "0" to "1", so that the terminal C becomes "1". Therefore, as shown in FIG. 2B, the clock waveform output from the terminal C of the flip-flop 14 rises from a low level to a high level.

Next, the value of the clock 100 falls to V2
Below this, the output of the operational amplifier 11 becomes low level, so that the terminals A and B of the flip-flop 14 become "0" and "0" as shown in the truth table of FIG. If only a certain terminal A changes from “1” to “0”, the terminal C of the flip-flop 14 does not change.
"1" is maintained.

Thereafter, when the value of the clock 100 further decreases and becomes equal to or less than V1, the output of the operational amplifier 12 becomes low level, so that the terminals A and B of the flip-flop 14 as shown in the truth table of FIG. Becomes "0" and "1". At this time, the terminal B, which is the set terminal, changes from “0” to “1”, so that the terminal C of the flip-flop 14 becomes “0”.
Changes to

Next, the value of the clock 100 rises and V
When the voltage is equal to or more than 1 and equal to or less than V2, the output of the operational amplifier 12 becomes high level, so that the terminals A and B of the flip-flop 14 become "0" and "1" as shown in the truth table of FIG. At this time, the terminal B, which is the set terminal, changes from “1” to “0”.
Does not change and remains "0". The same applies hereinafter.
From the terminal C of the flip-flop 14, a rectangular clock 104 as shown in FIG.

The counter 16 receives an input clock 104.
Is counted up to a predetermined value, and the warm-up signal 103 is inverted to notify a logic circuit (not shown) of the end of the warm-up. The warm-up period can be set arbitrarily by changing the count-up value of the counter 16.

Here, since the clock 100 after the power is turned on is unstable and fluctuates with respect to the reference voltages V1 and V2 as shown in FIG. 4, the clock 100 crosses both or one of the reference voltages V1 and V2. If there is no clock 104, the clock 104 is not generated from the terminal C of the flip-flop 14, and FIG.
As shown in FIG. 7A, the terminal C of the flip-flop 14 is not operated until the clock stably crosses V1 and V2.
Thus, a rectangular clock 104 as shown in FIG. 2B is generated.

According to this embodiment, the clock 100 oscillated after the power is turned on is stabilized and the reference voltages V1 and V
If the waveform does not cross over 2, the clock 104 input to the counter 16 is not generated, so that the unstable waveform that fluctuates immediately after the start of oscillation as shown in FIG. 4 is eliminated, and is used for setting the warm-up period. Since the counter 16 counts the clock using the stable and reliable clock 104, a warm-up period with high accuracy can be set.

Furthermore, since the stabilized clock 104 is used, it is not necessary to divide the clock as in the prior art, and the number of stages of the counter section is reduced, and the warm-up period after turning on the power or releasing the stop mode is shortened. Can be done.

FIG. 5 is a circuit diagram showing a configuration according to an embodiment of the power-on reset circuit of the present invention. The power-on reset circuit includes voltage-dividing resistors R1, R2, and R3 that divide the power supply voltage VDD to generate reference voltages V1 and V2, and an operational amplifier 1 that compares the reference voltage V2 with the clock 100.
1, an operational amplifier 12 for comparing a reference voltage V1 with a clock 100, and an inverter 1 for inverting an output of the operational amplifier 12
3. A flip-flop 14 which receives the outputs of the operational amplifier 11 and the inverter 13 and generates a stable clock 104
, An boosting circuit 20 for receiving and boosting a clock 104 generated by the oscillation stabilizing circuit 15, and inverters 21 and 22 connected to the output side of the boosting circuit 20. . The oscillation stabilizing circuit 15
Performs the same operation with the same configuration as that shown in FIG.

Next, the operation of this embodiment will be described.
Unstable clock 100 oscillated at power-on etc.
Is stabilized by the oscillation stabilizing circuit 15 and FIG.
As shown in FIG. This clock 104 is input to the booster circuit 20 and is sequentially boosted. As shown in FIG. 6B, the booster circuit 20 steps up the output voltage 300 stepwise by the reference voltage Vr for each cycle of the input clock 104, and the boosted output voltage 300 is output to the inverter 21.

Therefore, an arbitrary reset time can be set by changing the number of clocks until reaching the predetermined voltage by changing the reference voltage Vr.

Since the output voltage 300 of the booster circuit 20 is equal to or lower than a predetermined value at the beginning of power-on, the inverter 21
Is at a high level, the output of the inverter 22 is at a low level, the reset signal 200 is at a low level, and a logic circuit (not shown) is reset.

Thereafter, when the output voltage of the booster circuit 20 reaches a predetermined value, the inverter 21 is inverted to a low level, and the inverter 22 is inverted to a high level. Thus, when the reset signal 200 goes high, the reset of the logic circuit (not shown) is released.

According to the present embodiment, when the rising of the power supply voltage is slow and the inverters 21 and 22 are not operating and in an undefined state, the clock 104 from the oscillation stabilizing circuit 15 is supplied to the booster circuit 20. Not entered. afterwards,
After the inverters 21 and 22 operate and the logic circuit is reset, the clock 104 is supplied to the booster circuit 20.
Is input and the boosting is started, so that a predetermined reset period can always be provided in the logic circuit, and the power-on reset function can always function effectively even when the rise of the power supply voltage is slow.

FIG. 7 is a circuit diagram showing a configuration according to an embodiment of the starting circuit of the present invention. The starting circuit of the present embodiment is constituted by the warming-up detecting circuit and the power-on reset circuit of the above-described embodiment, and the oscillation stabilizing circuit 15 is common, and shows an example in which the oscillation stabilizing circuit 15 is mounted on an LSI. The counter 16 is connected to the oscillation stabilizing circuit 15,
A warm-up detecting circuit is configured, a boosting circuit 20, inverters 21 and 22 are connected to the oscillation stabilizing circuit 15, and a power-on reset circuit is configured. The operations of the respective circuits are the same as those described in each embodiment. . Warm-up signal 10 of warm-up detection circuit
3 is input to the logic circuit 80 of the LSI, and the reset signal 200 of the power-on reset circuit is also input to the logic circuit 80 of the LSI.

Next, the operation of this embodiment will be described with reference to FIG. As shown in FIG. 8A, the power supply voltage VDD
8B, the clock 100 oscillated from a clock oscillation circuit (not shown) initially has a small amplitude and fluctuates as shown in FIG. 8B, but the oscillation stabilizing circuit 15 removes an unstable portion on this side. , FIG.
A stable clock 104 is obtained as shown in FIG. This clock 104 is input to the counter 16 and the booster circuit 20. Therefore, both the warm-up detection circuit and the power-on reset circuit count the warm-up period 60 after the stable clock 104 starts to be input, and set the reset period 50.

In particular, the booster circuit 20 of the power-on reset circuit starts the operation of FIG.
As shown in FIG. 8D, boosting is started, and when the voltage reaches VIH a predetermined time after the start of boosting, the reset signal 200 becomes high level and the reset is released, as shown in FIG. Therefore, the predetermined reset period 50 can always be set even if the rise of the power supply voltage VDD is late.

In addition, since both the warm-up period 60 and the reset period 50 can be set with high accuracy, if the warm-up period 60 is set in advance so as to be shorter than the reset period 50, regardless of the rising speed of the power supply voltage, The warm-up period 60 can be made shorter than the reset period 50, so that even when the reset of the logic circuit 80 is released, the problem of the warm-up period can be eliminated, and the circuit is activated so that the logic circuit 80 does not malfunction. be able to.

The present invention is not limited to the above-described embodiment, and may be embodied in various other forms with specific configurations, functions, functions, and effects without departing from the gist thereof. .

[0036]

As described above in detail, according to the present invention, the reset period of the logic circuit is always constant regardless of the rise time of the power supply, and the reset period is always longer than the warm-up period. Can be
In addition, fluctuations can be removed from the clock waveform during the warm-up period, and a highly accurate warm-up period can be set.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of a warm-up detection circuit of the present invention.

FIG. 2 is a waveform chart showing waveform examples of a clock 100 and a stabilized clock 104 shown in FIG.

FIG. 3 is a truth table illustrating an operation of a flip-flop of the oscillation stabilizing circuit illustrated in FIG. 1;

FIG. 4 is a waveform diagram illustrating an unstable state of a clock 100 shown in FIG. 1;

FIG. 5 is a circuit diagram showing a configuration according to an embodiment of the power-on reset circuit of the present invention.

6 is a waveform diagram showing a relationship between a clock input to the booster circuit shown in FIG. 5 and an output voltage of the booster circuit 20.

FIG. 7 is a circuit diagram showing a configuration according to an embodiment of a starter circuit of the present invention.

FIG. 8 is a timing chart illustrating an operation of the startup circuit shown in FIG. 7 when the power supply voltage rises slowly.

FIG. 9 is a block diagram showing a configuration example of a conventional warm-up detection circuit.

FIG. 10 is a circuit diagram showing a configuration example of a conventional power-on reset circuit.

FIG. 11 is a timing chart illustrating the operation of a conventional power-on reset circuit and a conventional warm-up detection circuit when the power supply rises slowly.

[Description of Signs] 11, 12 Operational Amplifiers 13, 21, 22 Inverter 14 Flip-flop 15 Oscillation Stabilization Circuit 16 Counter 20 Boosting Circuit 80 Logic Circuit R1, R2, R3 Voltage Dividing Resistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX21 AX57 AX60 AX61 AX65 BX41 EX02 EY01 EZ00 EZ09 EZ31 EZ34 FX31 FX32 GX01 GX02 GX04 GX05

Claims (5)

[Claims] An input clock having a first reference voltage and a second reference voltage is synchronized with the input clock when the input clock is input across the first and second reference voltages. An oscillation stabilization circuit that generates a stabilized clock having a rectangular wave shape, a counter that counts the stabilization clock generated by the oscillation stabilization circuit, and inverts an output signal when a count value reaches a predetermined value; A warm-up detection circuit, comprising: 2. The warm-up detecting circuit according to claim 1, wherein the warm-up detecting circuit is formed in an integrated circuit, and sets a warm-up period of a logic circuit in the integrated circuit by changing a polarity of an output signal of the counter. Warm-up detection circuit. 3. When the input clock has a first reference voltage and a second reference voltage and is input across the first and second reference voltages, the input clock is synchronized with the input clock. An oscillation stabilizing circuit for generating a stabilized clock having a rectangular wave shape, a stabilizing clock generated by the oscillation stabilizing circuit, and an output voltage synchronized with a cycle of the input clock.
A power-on reset circuit, comprising: a booster circuit for sequentially boosting for each reference voltage; and at least one or more inverters for inputting an output voltage of the booster circuit. 4. The power-on reset circuit according to claim 3, wherein the power-on reset circuit is formed in an integrated circuit, and sets a reset period of a logic circuit in the integrated circuit by changing a polarity of an output signal of the inverter. A power-on reset circuit as described. 5. When the input clock has a first reference voltage and a second reference voltage and is input across the first and second reference voltages, the input clock is synchronized with the input clock. An oscillation stabilization circuit that generates a stabilized clock having a rectangular wave shape, a counter that counts the stabilization clock generated by the oscillation stabilization circuit, and inverts an output signal when a count value reaches a predetermined value; A stabilizing clock generated by the oscillation stabilizing circuit is input, and an output voltage is synchronized with a period of the input clock by a third clock.
An integrated circuit comprising: a booster circuit for sequentially boosting for each reference voltage; and at least one or more inverters for inputting an output voltage of the booster circuit. A warm-up period for a logic circuit in the integrated circuit, and a reset period for the logic circuit in the integrated circuit according to a change in polarity of an output signal of the inverter.