JPS62186345A - Microprocessor i/o address circuit - Google Patents

Abstract

PURPOSE:To easily increase number of I/O addresses without expanding the circuit scale remarkably by providing a decoder decoding an address signal of a microcomputer and a strap circuit leading its output to an I/O processor into an I/O device. CONSTITUTION:A bus signal line 1 is connected to the microcomputer. An address signal on an address signal line 2 branched from the bus signal line 1 is decoded by a decoder 5, a required component is selected by the strap circuit 9 and sent to an I/O processor 6. Since a specific decoding output is inputted to an input circuit of a specific I/O processor by the operation of the strap 9, the function of the I/O processor 6 is selected by an address signal from the microcomputer. The I/O processor 6 selects an external input data signal line 10 to reset a flip-flop 8 after the line 10 is finished being set to the data bus signal line 3 thereby having only to restart the operation of the microcomputer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to the I/O
This invention relates to an address detection circuit.

(Prior Art) Conventionally, the identification of the F/O address of a microcomputer involves inputting a plurality of address switches for setting an I/O number in an I/O device and an address signal output from the microcomputer main body. The device is equipped with an input circuit such as an I/O grosser for the input circuit, and a plurality of comparators for comparing the two, and determines whether or not the address information matches the switch setting value. Furthermore, the current situation is that circuits that perform such operations are placed in parallel as many times as necessary within one I/O device.

FIG. 2 is a block diagram showing an example of such a conventional I/O address circuit. In Figure 2, 121
123 are comparators, 41'3'1 to 133 are address switches, and 15 is an I/O processor.

In FIG. 2, address bus signals of path signal lines 11 of a microcomputer (not shown) are taken in by comparators 121 to 123, and address switches 131 to
133. When the above two match, the I/O signal is sent via the signal line 14 as a match signal.
It is taken into the O processor Is (which may be a specific logic circuit).

In the I/O processor 15, necessary external data signal lines, 1
6 is selected and output onto the data bus signal line 17. Second
The system shown in the figure requires a plurality of address switches and comparators depending on the number of required I/O numbers.

(Problems to be Solved by the Invention) The conventional method for identifying I/O addresses of microcomputers described above requires a set of address switches and a comparator for each I/O address identification. Met.

Therefore, in the conventional method, in order to identify multiple I/O addresses, multiple sets of address switches and comparators are required, even if it is simply estimated, so the number of addresses to be identified is extremely large. A system with a large number of parts has the disadvantage of being uneconomical due to the large number of parts used.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above disadvantages by providing a decoder for decoding the address of a microcomputer in an I/O device and a strap circuit for guiding its output to an I/O processor. An object of the present invention is to provide a microprocessor/O address circuit configured as follows.

(Preliminary means to solve the problem) The microprocessor I/O address circuit according to the present invention has the following features:
a decoder, a strap circuit, a wait request means, an I/
It is configured to include an O processor.

The decoder receives I/O from the microcomputer.
It is possible to decode as many pieces of '0 address information as necessary.

The strap circuit is for selecting the output of the decoder and directing it to the input circuit of the I/O processor.

The wait request means is for requesting a temporary stop of the processing of the microcomputer using the decoded signal selected by the strap circuit.

An I/O processor is used to perform processing within an I/O device.

In the above configuration, the address information outputted along with the input/output operation of the microcomputer is decomposed into N outputs by a decoder inside the E/O device. At this time, the number of outputs N of the decoder indicates the number of I/Os required for the system, and such a decoder can be easily constructed using an integrated circuit. Since the trap circuit is connected to the input circuits divided by function of the I/O processor, the decoder output signal corresponding to the I/O number required for the I/O device is sent to the I/O processor. Serves as input/output function designation signal. The wait request means is intended to overcome the slow processing speed of the I/O processor, and sends a wait request to the microcomputer body using the decoder output signal selected by the strap circuit. The request is released when the O processor is ready for the corresponding input/output data.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a microprocessor/O address circuit according to the present invention. In FIG. 1, S is a decoder, 6 is an I/O processor, F is an OR gate, 8 is a tree flop, and 9 is a strap circuit.

In FIG. 1, a path signal line l is connected to a microcomputer (not shown).

An address signal on a nine address signal line 2 branched from a bus signal line 1 is decoded by a decoder 5, and necessary components are selected by a strap circuit 9 and transmitted to an I/O processor 6.

The I/O processor 6 has M input circuits (M: positive integer), and each input circuit is assigned a different function. Therefore, due to the action of strut 9,
Since a particular decoding output is input to a particular I/O processor input circuit, an address signal from the microcomputer will select an I/O processor 60 function.

In this embodiment, M inputs are selected and the data bus signal line 3 is
However, in general, the operation speed of a processor is slower than that of a pure hardware logic circuit, so by outputting correct data onto the data bus signal line 3, the input operation of the microcomputer can be temporarily stopped using the flop flop. Must be requested by 8.

The clip-flop 8 is set by the input signal of the I/O processor 6. After the I/O processor 6 selects the external input data signal line /O and sets it to the data bus signal line 3, the flip-flop 8 is reset to restart the operation of the microcomputer. In this way, by extracting address signals based on I/O commands issued from the microcomputer using the decoder 5 and the strap circuit 9, an I/O address circuit of a microcomputer having multiple address selection functions can be easily configured. can.

(Effects of the Invention) As explained above, the present invention provides a decoder for decoding the address signal of the microcomputer and a strap circuit for guiding the output to the I/O processor in the engineering/O device. This has the effect that the number of I/O addresses can be easily increased without significantly increasing the circuit scale.

Additionally, if the I/O device is constructed on a single standard size printed circuit board, the present invention requires only one IC and 16 pairs of strap terminals to decode 16 pairs of I/O addresses. It has the effect of finishing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a microprocessor/O address circuit according to the present invention. FIG. 2 is a block diagram showing an example of an I/O address circuit according to the prior art. 5. Decoder 6.15--I/O grosser 7-Fist-OR gate 8--Clip flop 9+1--Strap circuit 121-123--Comparator

Claims (1)

[Claims] a decoder for decoding a required number of I/O address information from the microcomputer; a strap circuit for selecting the output of the decoder and guiding it to the input circuit of the I/O processor; A microprocessor I/O address comprising a wait request means for requesting a temporary stop of processing of the microcomputer by a decoded signal, and an I/O processor for performing internal processing. circuit.