JPH10143364A - Processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a user define an original command without adding any change to a processor core optimally designed by providing a 1st command decoder for decoding a non-user-defined command in the processor core and providing a 2nd command decoder for decoding a user-defined command in a user's original circuit. SOLUTION: Since the user a original circuit 8 is provided with the 2nd command decoder 12 for decoding a user-defined command, the 1st command decoder 10 for decoding a non-user-defined command is made having no concern in any content of the user-defined command. Thus, even if the content of the user-defined command differs for each user, it is not required to design the 1st command decoder 10 again. Thus, by previously building in a command usable as the user-defined command in the command set of the processor core 7, a peculiar command can be defined without adding any change to the processor core 7 optimally designed by full-custom design.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU (central
processing unit) or DSP (digital signal process)
The present invention relates to a processing device in which a user-specific circuit uniquely designed by a user is integrated on a single chip together with a processor such as (or).

[0002] With the development of fine processing technology for semiconductor devices,
The circuit scale mounted on the semiconductor chip increases,
A so-called system ASI, in which a user-specific circuit is mounted on a single chip together with a microprocessor (microcontroller) such as a U or a DSP to form a fixed system.
C (application specific IC) is being developed.

[0003]

2. Description of the Related Art FIG. 11 is a block diagram showing an essential part of an example of a conventional system ASIC. In FIG. 11, 1 is a chip body, 2 is a processor core such as a CPU or DSP, and 3 is a ROM (read only). memory), 4 is RAM (random acc
ess memory), 5 is a user-specific circuit uniquely designed by the user.

Here, the instruction set of the processor core 2 prepares instructions that a designer of the processor core 2 considers necessary in advance, and a system ASIC developer designs a system within the range. There is a need.

[0005]

The system A
It would be very convenient if the designer of the SIC could add its own instructions to the instruction set of the processor core 2, but in order to do this, it was necessary to map the instructions to be added to the instruction set. As a result, the instruction decoder needs to be redesigned.

However, in general, the processor core 2
Since it has been optimized by full custom design to achieve high performance and small area, if the instruction decoder is redesigned, it is not enough, and the entire processor core 2 must be redesigned. This leads to higher prices.

In view of the foregoing, the present invention provides a processing device that allows a user to define a unique instruction without changing a processor core optimally designed by full custom design. With the goal.

[0008]

According to a first aspect of the present invention, there is provided a processor core having a non-user-defined instruction execution unit for executing a non-user-defined instruction; And a user-specific circuit having a user-defined instruction execution unit for executing a first instruction decoder for decoding a non-user-defined instruction in a processor core and a second instruction for decoding a user-defined instruction in a user-specific circuit. It has an instruction decoder.

According to the first aspect of the present invention, the second instruction decoder for decoding the user-defined instruction is provided in the user-specific circuit. Can be prevented from being noticed at all, so that there is no need to redesign the first instruction decoder even if the content of the user-defined instruction differs for each user.

Therefore, by incorporating in advance the instructions that can be used as user-defined instructions into the instruction set of the processor core, the processor core optimally designed by the full custom design is not changed, and The user can define his own instructions for the instructions that can be used as user-defined instructions.

According to a second aspect of the present invention, in the first aspect, the first instruction decoder and the second instruction decoder execute the same instruction in parallel via a common bus. The first instruction decoder has a function of identifying whether or not the fetched instruction is a user-defined instruction, and the second instruction decoder identifies that the first instruction decoder is a user-defined instruction. The instruction is configured to be recognized as a user-defined instruction.

In a third aspect of the present invention, the processing apparatus according to the third aspect has a one-word user-defined instruction in the second invention, and the one-word user-defined instruction is It has an instruction field in which an instruction code indicating a definition instruction and a word length is entered, and an instruction field in which an instruction code indicating the type of instruction is entered.

Therefore, in the third invention, the first invention
When the instruction decoder fetches a user-defined instruction consisting of one word, the instruction decoder recognizes that the fetched instruction is a user-defined instruction and recognizes the word length from the user-defined instruction and the instruction code indicating the word length. It is configured to output a detection signal to the second instruction decoder and then stop taking in the next instruction until receiving a user-defined instruction execution completion signal from the second instruction decoder.

When the second instruction decoder receives a user-defined instruction consisting of one word and receives a user-defined instruction detection signal from the first instruction decoder, the second instruction decoder recognizes the fetched instruction as a user-defined instruction. The word length of the fetched user-defined instruction is recognized from the user-defined instruction and the instruction code indicating the word length, and when the execution of the user-defined instruction is completed by the user-defined instruction execution unit, a user-defined instruction execution completion signal is output. It is configured to output to one instruction decoder.

According to a fourth aspect of the present invention, in the processing apparatus according to the fourth aspect, there is provided a user-defined instruction comprising a plurality of words. The word has an instruction field in which a user-defined instruction and an instruction code indicating a word length are written, and an instruction field in which an instruction code indicating a type of the instruction is written.

Therefore, in the fourth invention, the first
When fetching the first word of a user-defined instruction consisting of a plurality of words, the instruction decoder recognizes that the fetched instruction is a user-defined instruction and the word length from the user-defined instruction and the instruction code indicating the word length. Each time the second and subsequent words are fetched in sequence, and each time the first and subsequent words are fetched, a user-defined instruction detection signal is output to the second instruction decoder. The reception of the next instruction is stopped until a user-defined instruction execution completion signal is received from the decoder.

When the first instruction decoder receives a user-defined instruction detection signal from the first instruction decoder when the first word of the user-defined instruction consisting of a plurality of words is fetched, the second instruction decoder converts the fetched instruction into a user instruction. It recognizes as a definition instruction, recognizes the word length of the fetched user-defined instruction from the instruction code indicating the user-defined instruction and the word length, and receives the second or later user-defined instruction detection signal from the first instruction decoder every time the second instruction is received. A word fetched in parallel with one instruction decoder is processed as a word of a user-defined instruction, and when the user-defined instruction execution unit completes execution of the user-defined instruction, the first instruction decoder sends a user-defined instruction execution completion signal to the first instruction decoder. It is configured to output.

According to a fifth aspect of the present invention, in the processing apparatus according to the fourth aspect, the instruction code indicating a user-defined instruction is provided for each user-defined instruction having a different word length. And an instruction code indicating a word length.

According to a sixth aspect of the present invention, in the second aspect of the present invention, there is provided a processing device having a one-word user-defined instruction. It has an instruction field in which an instruction code indicating a definition instruction is entered, and an instruction field in which an instruction code indicating a word length and an instruction type is entered.

Therefore, in the sixth invention, the first
When the instruction decoder fetches a user-defined instruction consisting of one word, the instruction decoder recognizes that the fetched instruction is a user-defined instruction, outputs a user-defined instruction detection signal to the second instruction decoder, and outputs the second instruction decoder. , The acquisition of the next instruction is stopped until a user-defined instruction execution completion signal is received.

When the second instruction decoder receives the user-defined instruction detection signal from the first instruction decoder, the second instruction decoder recognizes the word fetched in parallel with the first instruction decoder as a user-defined instruction, and determines the word length and the instruction length. From the instruction code indicating the type, the fetched word is recognized and processed as a one-word user-defined instruction, and when the user-defined instruction execution unit completes execution of the user-defined instruction, a user-defined instruction execution completion signal is output. It is configured to output to a first instruction decoder.

According to a seventh aspect of the present invention, there is provided the processing apparatus according to the sixth aspect, further comprising a user-defined instruction comprising a plurality of words. The word has an instruction field in which an instruction code indicating a user-defined instruction is written, and an instruction field in which an instruction code indicating a word length and an instruction type is written. Has an instruction field in which an instruction code indicating a user-defined instruction is entered.

Therefore, in the seventh invention, the first
The instruction decoder recognizes that the instruction is a user-defined instruction from an instruction code indicating that the instruction is a user-defined instruction, and outputs a user-defined instruction detection signal to the second instruction every time each word of the user-defined instruction composed of a plurality of words is taken. Each time it outputs to the decoder and outputs a user-defined instruction detection signal to the second instruction decoder, the acquisition of the next word is stopped until a user-defined instruction execution completion signal is received from the second instruction decoder. .

When the second instruction decoder receives the first user-defined instruction detection signal from the first instruction decoder, the second instruction decoder determines from the instruction code indicating the word length and the type of the instruction.
Recognizing the word length of the fetched user-defined instruction,
Until a user-defined instruction detection signal corresponding to the capture of the last word is received from the instruction decoder, a user-defined instruction execution completion signal is generated every time the user-defined instruction detection signal is received, even though the user-defined instruction has not been executed. Each time a user-defined instruction detection signal is output from the first instruction decoder and received from the first instruction decoder, a word fetched in parallel with the first instruction decoder is recognized and processed as a user-defined instruction, and the user-defined instruction is executed. When the unit completes execution of the user-defined instruction, the unit outputs a user-defined instruction execution completion signal to the first instruction decoder.

According to an eighth aspect of the present invention, in the processing apparatus according to the seventh aspect, the instruction code indicating a user-defined instruction is one type of instruction code regardless of the word length. The instruction code indicating the word length also serves as an instruction code indicating the type of instruction.

According to a ninth aspect of the present invention, in the ninth aspect of the present invention, there is provided the processing apparatus according to the seventh aspect, further comprising an interrupt suppressing circuit for suppressing the input of the interrupt signal while the interrupt suppressing signal is being supplied. When the second instruction decoder fetches the first word of the user-defined instruction composed of a plurality of words, the second instruction decoder is configured to supply an interrupt suppression signal to the interrupt suppression circuit until the fetch of the last word is completed. Things.

In the seventh aspect of the present invention, when the first instruction decoder fetches a user-defined instruction including a plurality of words, the first instruction decoder recognizes that the fetched user-defined instruction is a user-defined instruction having a plurality of words. In some cases, an interrupt may occur while a plurality of words of a user-defined instruction are being fetched. However, according to the ninth aspect, since an interrupt suppression circuit is provided, a plurality of words of a user-defined instruction are provided. Even if an interrupt occurs during the fetching of an instruction, this can be suppressed.

According to a tenth aspect of the present invention, in the first aspect, the first instruction decoder and the second instruction decoder execute the same instruction in parallel via a common bus. When the second instruction decoder fetches a user-defined instruction, the second instruction decoder recognizes the fetched instruction as a user-defined instruction from an instruction code indicating that the instruction is a user-defined instruction regardless of the first instruction decoder. It is configured as follows.

According to the tenth aspect, the same operation as that of the first aspect can be obtained, and a circuit for outputting a user-defined instruction detection signal to the first instruction decoder is not required.

According to an eleventh aspect of the present invention, in the tenth aspect of the present invention, the second instruction decoder is configured such that when the user-defined instruction execution unit completes execution of the user-defined instruction, , And outputs a user-defined instruction to the first instruction decoder. When the first instruction decoder receives the user-defined instruction, the first instruction decoder stops receiving the next instruction until it receives a user-defined instruction execution completion signal. That is.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
First, second, and third embodiments of the present invention will be described.

1 to 5 FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention. In FIG. 1, reference numeral 7 denotes a processor core such as a CPU or DSP;
Reference numeral 8 denotes a user-specific circuit uniquely designed by the user, and 9 denotes a bus.

In the processor core 7, reference numeral 10 denotes a first instruction decoder which detects a user-defined instruction and decodes a non-user-defined instruction, and 11 denotes a first instruction decoder.
Is a non-user-defined instruction execution unit that executes the non-user-defined instruction decoded in step (1).

In the user-specific circuit 8, reference numeral 12 denotes a second instruction decoder for recognizing a user-defined instruction in response to a user-defined instruction detection signal from the first instruction decoder 10 and decoding the recognized user-defined instruction.
Is a user-defined instruction execution unit for executing the user-defined instruction decoded by the second instruction decoder 12.

The same instruction is supplied to the first instruction decoder 10 and the second instruction decoder 12 via the bus 9.
The first instruction decoder 10 is configured to support the non-user-defined instructions shown in FIG. 2 and the user-defined instructions shown in FIGS. 3 to 5, and the second instruction decoder 12 is configured to correspond to the instructions shown in FIGS. It is configured to be able to respond to user-defined instructions.

FIG. 2 is a diagram showing the format of a non-user-defined instruction consisting of one word (16 bits) used in the first embodiment of the present invention, where the upper 5 bits are the instruction field and the lower 11 bits are the instruction field. It is an operand field, and an instruction code indicating the type of instruction is written in the instruction field.

FIGS. 3 to 5 show a first embodiment of the present invention.
FIG. 3 is a diagram showing a format of a user-defined instruction used in the embodiment, FIG. 3 shows a case of a user-defined instruction composed of one word, FIG. 4 shows a case of a user-defined instruction composed of two words, and FIG. This shows the case of a definition instruction.

A user-defined instruction consisting of one word has a first instruction field in the upper 5 bits, a second instruction field in the middle 3 bits, and an operand field in the lower 8 bits. An instruction field in which an instruction code indicating a definition instruction is entered is set, and a second instruction field is an instruction field in which an instruction code indicating an instruction type is entered.

In the user-defined instruction consisting of two words, for the first word, the upper five bits are the first instruction field, the middle three bits are the second instruction field, and the lower eight bits are the lower eight bits.
Bits are used as an operand field, and for the second word, the entire 16 bits are used as an operand field. The first instruction field is an instruction field in which an instruction code indicating a two-word user-defined instruction is written. The instruction field is an instruction field in which an instruction code indicating the type of instruction is written.

For a user-defined instruction consisting of three words, for the first word, the upper 5 bits are the first instruction field, the middle 3 bits are the second instruction field, and the lower 8 bits.
An instruction field in which bits are an operand field, a second word and a third word, an entire 16 bits are an operand field, and the first instruction field is an instruction field in which an instruction code indicating a three-word user-defined instruction is entered. The second instruction field is an instruction field in which an instruction code indicating the type of instruction is written.

In this example, the instruction field of the non-user-defined instruction contains "1F" as an instruction code indicating the type of the instruction.
₁₆ "," 1E ₁₆ "and" 1D ₁₆ "are based on the assumption that never used, the instruction code indicates a user-defined command consisting of one word" 1F ₁₆ ", a user-defined instructions consisting of two words The instruction code indicated is “1E ₁₆ ”, and the instruction code indicating a three-word user-defined instruction is “1E ₁₆ ”.
D ₁₆ ".

In this example, since the second command field indicating the command type of the user-defined command has 3 bits, up to eight user-defined commands can be defined.

Therefore, in the first embodiment of the present invention, the first instruction decoder 10 is configured to perform the following operation.

That is, whether or not the fetched instruction is a user-defined instruction is identified from the contents of the upper 5 bits of the fetched instruction. If the fetched instruction is a non-user-defined instruction, the non-user-defined instruction is decoded. If the instruction is a user-defined instruction, the word length of the user-defined instruction is recognized from the instruction code written in the first instruction field.

When the fetched instruction is a user-defined instruction and the word length is one word, a user-defined instruction detection signal is output to the second instruction decoder 12, and the second instruction decoder 12 Stop fetching the next instruction until receiving the definition instruction execution completion signal.

On the other hand, when the word length of the fetched user-defined instruction is two words, the first-time user-defined instruction detection signal is output to the second instruction decoder 12 when the first word is fetched. Then, the second word is fetched, a second user-defined instruction detection signal is output to the second instruction decoder 12, and the next instruction is fetched until a user-defined instruction execution completion signal is received from the second instruction decoder 12. Stop.

If the word length of the fetched user-defined instruction is 3 words, the first-time user-defined instruction detection signal is output to the second instruction decoder 12 when the first word is fetched. Fetch the second word,
The second user-defined instruction detection signal is sent to the second instruction decoder 12
, And then fetches the third word, outputs a third user-defined instruction detection signal to the second instruction decoder 12, and outputs the next instruction until a user-defined instruction execution completion signal is received from the second instruction decoder 12. Stop importing.

On the other hand, the second instruction decoder 12 is configured to perform the following operation. That is, when a user-defined instruction detection signal is received from the first instruction decoder 10, an instruction fetched in parallel with the first instruction decoder 10 is recognized as a user-defined instruction.
The instruction code in the first instruction field is decoded, the word length of the user-defined instruction is recognized, and the instruction code in the second instruction field indicating the type of the instruction is decoded.

Here, when the word length of the user-defined instruction is one word, it is processed as a one-word user-defined instruction, and when the execution of the user-defined instruction in the user-defined instruction execution unit 13 is completed, It outputs a user-defined instruction execution completion signal to the first instruction decoder 10.

On the other hand, when the word length of the user-defined instruction is two words, the first instruction decoder 10 waits for the output of a second user-defined instruction detection signal, and
When the second user-defined instruction detection signal is input, all the fields of the second word fetched in parallel with the first instruction decoder 10 are processed as the remaining operand fields of the two-word user-defined instruction. When the execution of the user-defined command is completed in the definition command execution unit 13, a user-defined command execution completion signal is sent to the first
Output to the instruction decoder 10.

When the word length of the user-defined instruction is 3 words, the first instruction decoder 10 waits for the output of the second user-defined instruction detection signal, and outputs the second user-defined instruction detection signal. In the case of input, all fields of the second word fetched in parallel with the first instruction decoder 10 are replaced with two words of the user-defined instruction consisting of three words.
Process as word operand field.

Then, further, it waits for the third user-defined instruction detection signal to be output from the first instruction decoder 10 and, when the third user-defined instruction detection signal is input, together with the first instruction decoder 10. All the fields of the third word fetched in parallel are processed as the remaining operand fields of the user-defined instruction consisting of three words. When the execution of the user-defined instruction is completed in the user-defined instruction execution unit 13, the user-defined instruction is executed. An instruction execution completion signal is output to the first instruction decoder 10.

The first embodiment of the present invention configured as described above
In the embodiment, at the time of fetching an instruction, the same instruction is transmitted via the bus 9 to the first instruction decoder 10 and the second instruction decoder 1.
2 is supplied.

Here, if the instruction supplied to the first instruction decoder 10 and the second instruction decoder 12 is a non-user-defined instruction, the first instruction decoder 10 decodes the non-user-defined instruction, and The definition instruction execution unit 11 executes the non-user-defined instruction decoded by the first instruction decoder 10.

On the other hand, when the instruction supplied to the first instruction decoder 10 and the second instruction decoder 12 is a user-defined instruction consisting of one word, the first instruction decoder 10
Identifies that the fetched instruction is a one-word user-defined instruction from the content "1F ₁₆ " of the first instruction field, outputs a user-defined instruction detection signal to the second instruction decoder 12, and outputs Stop importing.

Here, when receiving the user-defined instruction detection signal from the first instruction decoder 10, the second instruction decoder 12 recognizes the instruction fetched in parallel with the first instruction decoder 10 as a user-defined instruction. , The instruction code in the second instruction field, and the user-defined instruction execution unit 13 executes the user-defined instruction consisting of one word decoded by the second instruction decoder 12.

When the execution of the user-defined instruction consisting of one word in the user-defined instruction execution unit 13 is completed, the second instruction decoder 12 outputs a user-defined instruction execution completion signal to the first instruction decoder 10, and When receiving the user-defined instruction execution completion signal, the instruction decoder 10 releases the stop of taking in the next instruction.

When the instruction supplied to the first instruction decoder 10 and the second instruction decoder 12 is a user-defined instruction consisting of two words, the first instruction decoder 10
From the content of the instruction field “1E ₁₆ ”, it is identified that the fetched instruction is a two-word user-defined instruction, and a user-defined instruction detection signal is output to the second instruction decoder 12.
Subsequently, the second word is fetched, a second user-defined instruction detection signal is output to the second instruction decoder 12, and the fetch of the next instruction is stopped.

When the second instruction decoder 12 receives the first user-defined instruction detection signal from the first instruction decoder 10, the second instruction decoder 12 fetches the instruction fetched in parallel with the first instruction decoder 10 into the user-defined instruction. And the first
The first instruction decoder 10 decodes the instruction code in the instruction field and recognizes that the instruction is a two-word instruction.
It waits for the second user-defined command detection signal to be output.

When the second instruction decoder 12 receives the second user-defined instruction detection signal from the first instruction decoder 10, the second instruction decoder 12 processes all fields of the second word as the remaining operand fields of the user-defined instruction. The user-defined instruction execution unit 13 executes a user-defined instruction consisting of two words decoded by the second instruction decoder 12.

Further, the second instruction decoder 12
When the execution of the two-word user-defined instruction in the user-defined instruction execution unit 13 is completed, a user-defined instruction execution completion signal is output to the first instruction decoder 10, and the first instruction decoder 10 outputs the user-defined instruction execution completion signal. If it has been received, it stops releasing the next instruction.

When the instruction supplied to the first instruction decoder 10 and the second instruction decoder 12 is a user-defined instruction consisting of three words, the first instruction decoder 10
Based on the contents of the instruction field “1D ₁₆ ”, it is identified that the fetched instruction is a three-word user-defined instruction, and a first user-defined instruction detection signal is output to the second instruction decoder 12. And outputs a second user-defined instruction detection signal to the second instruction decoder 12,
Then, the third word is fetched, a third user-defined instruction detection signal is output, and the fetch of the next instruction is stopped.

On the other hand, when receiving the first user-defined instruction detection signal from the first instruction decoder 10, the second instruction decoder 12 recognizes the instruction fetched simultaneously with the first instruction decoder 10 as a user-defined instruction. , Decodes the instruction code in the first instruction field, recognizes that the instruction is a three-word instruction, and waits for the first instruction decoder 10 to output the second user-defined instruction detection signal.

When receiving the second user-defined instruction detection signal from the first instruction decoder 10, the second instruction decoder 12 treats all fields of the second word as operand fields of the user-defined instruction. 1
Waiting for the third user-defined instruction detection signal to be output from the instruction decoder 10, and receiving the third user-defined instruction detection signal from the first instruction decoder 10, all the fields of the third word are composed of three words. The instruction is processed as the remaining operand field of the user-defined instruction, and the user-defined instruction execution unit 13 executes the user-defined instruction consisting of three words decoded by the second instruction decoder 12.

Further, the second instruction decoder 12
When the execution of the three-word user-defined instruction in the user-defined instruction execution unit 13 is completed, a user-defined instruction execution completion signal is output to the first instruction decoder 10, and the first instruction decoder 10 outputs the user-defined instruction execution completion signal. After receiving, release of the fetch of the next instruction is released.

As described above, according to the first embodiment of the present invention, the first instruction decoder 10 provided in the processor core 7 detects a user-defined instruction. Since there is no concern, there is no need to redesign the first instruction decoder 10 even if the content of the user-defined instruction differs for each user.

Therefore, by incorporating in advance the instructions that can be used as user-defined instructions into the instruction set of the processor core 7, the processor core 7 optimally designed by the full custom design is not changed. In addition, the user can define a unique command to a command that can be used as a user-defined command.

In the first embodiment of the present invention, each time the second instruction decoder 12 receives the user-defined instruction detection signal from the first instruction decoder 10, it decodes the instruction code of the user-defined instruction. However, instead of this, the second instruction decoder 12 may be configured to always decode the user-defined instruction supplied via the bus 9, and in such a case, In addition, the user-defined instruction detection signal is not required, and the first instruction decoder 10 does not require a user-defined instruction detection signal generation circuit.

6 to 9 FIG. 6 is a circuit diagram showing a main part of a second embodiment of the present invention. In the second embodiment of the present invention, Instead of the first instruction decoder 10 and the second instruction decoder 12 provided in the first embodiment, these first instruction decoders 10
And a first instruction decoder 15 and a second instruction decoder 16 which are different in circuit configuration from the second instruction decoder 12.

Here, in the second embodiment of the present invention, the user-defined instruction is configured as shown in FIG. 7 to FIG. 9, and the first instruction decoder 15 is provided with the non-user-defined instruction shown in FIG. The second instruction decoder 16 is configured so as to support the instruction and the user-defined instruction shown in FIGS.
To the user-defined instructions shown in FIGS.

FIGS. 7 to 9 are diagrams showing the format of a user-defined instruction used in the second embodiment of the present invention. FIG. 7 shows a case of a user-defined instruction consisting of one word, and FIG. In the case of a user-defined instruction consisting of words, FIG. 9 shows the case of a user-defined instruction consisting of three words.

The user-defined instruction consisting of one word has the upper 5 bits as the first instruction field, the middle 3 bits as the second instruction field, the lower 8 bits as the operand field, and the first instruction field as the user-defined instruction. The second instruction field is an instruction field in which an instruction code indicating a word length is written.

In the case of a user-defined instruction consisting of two words, for the first word, the upper 5 bits are the first instruction field, the middle 3 bits are the second instruction field, and the lower 8 bits.
Bits are an operand field, and for the second word, the upper 5 bits are a third instruction field, the lower 11 bits are an operand field, and an instruction code indicating that the first instruction field and the third instruction field are user-defined instructions is The instruction field to be entered and the second instruction field are instruction fields in which an instruction code indicating a word length is entered.

For a user-defined instruction consisting of three words, for the first word, the upper 5 bits are the first instruction field, the middle 3 bits are the second instruction field, and the lower 8
Bits as an operand field, and for the second word, the upper 5 bits are the third instruction field and the lower 11
Bits as an operand field, and for the third word, the upper 5 bits are the fourth instruction field and the lower 11
An instruction field in which bits are set as an operand field, and an instruction field in which an instruction code indicating a first instruction field, a third instruction field, and a fourth instruction field are user-defined instructions are written, and a second instruction field is an instruction indicating a word length. It is an instruction field in which a code is entered.

In this example, the instruction field of the non-user-defined instruction contains “1F” as an instruction code indicating the type of instruction.
₁₆ "is not used, and the instruction code indicating the user-defined instruction is set to" 1F ₁₆ "regardless of the word length.

Therefore, the one-word user-defined instruction is a one-word instruction in the second instruction field, "5 ₁₀ " is written as an instruction code indicating the instruction type, and the two-word user-defined instruction is written. Is a command consisting of two words in the second command field and "4 ₁₀ " as a command code indicating the command type, and a user-defined command consisting of three words is a command consisting of three words in the second command field. And “3 ₁₀ ” is entered as an instruction code indicating the instruction type.

Therefore, in the second embodiment of the present invention, the first instruction decoder 15 is configured to perform the following operation.

That is, whether or not the fetched instruction is a user-defined instruction is identified from the contents of the upper 5 bits of the fetched instruction. If the fetched instruction is a non-user-defined instruction, the non-user-defined instruction is decoded. .

On the other hand, when the word of the user-defined instruction is fetched, the word of the user-defined instruction is recognized from the instruction code “1F ₁₆ ” described in the upper 5 bits. The detection signal is output to the second instruction decoder 16, and the reception of the next word is stopped until a user-defined instruction completion signal is received from the second instruction decoder 16.

On the other hand, the second instruction decoder 16 is configured to perform the following operation. That is, when a user-defined instruction detection signal is received from the first instruction decoder 15, the instruction supplied in parallel with the first instruction decoder 15 is recognized as a user-defined instruction, and the second instruction field is decoded. To recognize the word length of the user-defined instruction.

If the word length of the user-defined instruction is one word, it is processed as a one-word user-defined instruction, and the execution of the one-word user-defined instruction in the user-defined instruction execution unit 13 is completed. In this case, a user-defined instruction execution completion signal is output to the first instruction decoder 15.

On the other hand, when the word length of the user-defined instruction is two words, the first instruction decoder 15 waits for the second user-defined instruction detection signal to be output, and then waits for the second user-defined instruction. When an instruction detection signal is input,
When the lower 11 bits of the second word fetched in parallel with the first instruction decoder 15 are processed as the remaining operand fields of the user-defined instruction, and the execution of the user-defined instruction consisting of two words is completed in the user-defined instruction execution unit 13 Contains a user-defined instruction execution completion signal as the first
Output to the instruction decoder 15.

If the word length of the user-defined instruction is three words, the first instruction decoder 15 waits for the second user-defined instruction detection signal to be output, and outputs the second user-defined instruction detection signal. When input, the lower 11 bits of the second word fetched in parallel with the first instruction decoder 15 are processed as the operand field of the second word of the user-defined instruction.

Then, it waits for the third user-defined instruction detection signal to be output from the first instruction decoder 15, and when the third user-defined instruction detection signal is input, the first
The lower 11 bits of the third word fetched in parallel with the instruction decoder 15 are processed as the remaining operand fields of the user-defined instruction, and the user-defined instruction execution unit 13
When the execution of the user-defined instruction consisting of three words is completed, a user-defined instruction execution completion signal is output to the first instruction decoder 15.

The second embodiment of the present invention configured as described above
In the embodiment, when the instruction is taken in, the same instruction is transmitted via the bus 9 to the first instruction decoder 15 and the second instruction decoder 1.
It is taken into 6.

Here, if the instructions fetched by the first instruction decoder 15 and the second instruction decoder 16 are non-user-defined instructions, the first instruction decoder 15 decodes the non-user-defined instructions and The definition command execution unit 11
The non-user-defined instruction decoded by the first instruction decoder 15 will be executed.

On the other hand, if the instructions fetched by the first instruction decoder 15 and the second instruction decoder 16 are words of a user-defined instruction, the second instruction decoder 16
From contents "1F _16" of the first instruction field, identifies that fetched instruction is a user-defined command, and outputs the user-defined instruction detection signal to the second instruction decoder 16, stop receiving the next word I do.

Here, when the second instruction decoder 16 receives the user-defined instruction detection signal, the content of the second instruction field of the user-defined instruction taken in parallel with the first instruction decoder 15 is "5 ₁₀ ". In the case of, the fetched instruction is recognized as a one-word instruction, and the instruction is decoded.
The second instruction decoder 16 executes the decoded user-defined instruction.

When the execution of the instruction in the user-defined instruction execution unit 13 is completed, the second instruction decoder 16
The first instruction decoder 15 outputs a user-defined instruction execution completion signal to the first instruction decoder 15, and after receiving the user-defined instruction execution completion signal, fetches the next instruction.

On the other hand, if the content of the second instruction field of the user-defined instruction fetched by the second instruction decoder 16 is “4 ₁₀ ”, the second instruction decoder 16 determines that the fetched instruction has two words. Recognizing that this is an order,
It outputs a user-defined instruction execution completion signal to the first instruction decoder 15.

As a result, the first instruction decoder 15 fetches the next word. In this case, since the third instruction field of the fetched word is "1F ₁₆ ", it is recognized as a user-defined instruction. Then, a second user-defined instruction detection signal is output to the second instruction decoder 16 to stop taking in the next word.

Here, when the second instruction decoder 16 receives the second user-defined instruction detection signal from the first instruction decoder 15, the second instruction decoder 16 converts the lower 11 bits of the word fetched simultaneously with the first instruction decoder 15 into the user instruction. Definition instruction 2
Treated as a word operand field, the user-defined instruction execution unit 13 executes a user-defined instruction consisting of two words.

The contents of the second instruction field of the user-defined instruction fetched by the second instruction decoder 16 are "3 ₁₀ ".
In this case, the second instruction decoder 16 recognizes that the fetched instruction is a three-word instruction, and outputs a user-defined instruction execution completion signal to the first instruction decoder 15.

As a result, the first instruction decoder 15 fetches the next word. In this case, since the first instruction field of the fetched word is “1F ₁₆ ”, it is recognized as a user-defined instruction. Then, a second user-defined instruction detection signal is output to the second instruction decoder 16 to stop taking in the next word.

When the second instruction decoder 16 receives the user-defined instruction detection signal, the second instruction decoder 16 converts the lower 11 bits of the word fetched simultaneously with the first instruction decoder 15 into the operand field of the second word of the user-defined instruction. And outputs a user-defined instruction execution completion signal to the first instruction decoder 15.

As a result, the first instruction decoder 15 fetches the next word. In this case, since the first instruction field of the fetched word is "1F ₁₆ ", it is recognized as a user-defined instruction. Then, a third user-defined instruction detection signal is output to the second instruction decoder 16 to stop fetching the next instruction.

Here, when the second instruction decoder 16 receives the third user-defined instruction detection signal, the second instruction decoder 16
The lower 11 words of the word fetched simultaneously with the instruction decoder 15
The bits are handled as the operand field of the third word of the user-defined instruction, and the user-defined instruction execution unit 13 executes the user-defined instruction consisting of three words.

When the execution of the three-word user-defined instruction is completed in the user-defined instruction execution unit 13, the second instruction decoder 16 outputs a user-defined instruction execution completion signal to the first instruction decoder 15. Become.

As described above, according to the second embodiment of the present invention, the first instruction decoder 15 provided in the processor core 7 detects a user-defined instruction. Since it does not matter, there is no need to redesign the first instruction decoder 15 even if the content of the user-defined instruction differs for each user.

Therefore, by incorporating in advance the instructions that can be used as user-defined instructions into the instruction set of the processor core 7, the processor core 7 that is optimally designed by full custom design is not changed. In addition, the user can define a unique command to a command that can be used as a user-defined command.

Third Embodiment FIG. 10 FIG. 10 is a circuit diagram showing a main part of a third embodiment of the present invention. The third embodiment of the present invention is similar to the second embodiment of the present invention.
Instead of the second instruction decoder 16 provided in the embodiment, the second instruction decoder 1 having a different circuit configuration from the second instruction decoder 16
8 and an interrupt suppression circuit 19 are provided, and the rest is configured in the same manner as the second embodiment of the present invention.

Here, the second instruction decoder 18 supplies an interrupt suppressing signal to the interrupt suppressing circuit 19,
Otherwise, the configuration is the same as that of the second instruction decoder 16.

The second instruction decoder 18 sets the interrupt suppression signal to H level when a user-defined instruction consisting of two or three words is input, and otherwise sets the interrupt suppression signal to L level. It is configured as follows.

In the interrupt suppressing circuit 19, 2
Reference numerals 0 to 22 denote logic circuits for controlling the passage of the interrupt signal by using the interrupt suppression signal as a gate signal. When the interruption suppression signal is at H level, the passage of the interruption signal is suppressed. When the interruption suppression signal is at L level, Pass the interrupt signal.

According to the third embodiment of the present invention, the same operation and effect as those of the second embodiment of the present invention can be obtained, and the first instruction decoder 15 can perform two-word or three-word user-defined operations. When the instruction is fetched, the interrupt is not recognized while the fetched user instruction is a two-word or three-word user-defined instruction because it is not recognized that the fetched user instruction is a two-word or three-word user-defined instruction. Although an interrupt may occur, the interrupt suppression circuit 19 is provided, so that even if an interrupt occurs while a two- or three-word user-defined instruction is being fetched, this can be suppressed. .

Note that, in the second and third embodiments of the present invention, the second instruction decoder 16
5 has been described in which the instruction code of the second instruction field of the user-defined instruction is decoded each time the user-defined instruction detection signal from the second instruction decoder 16 is received. In such a case, a user-defined instruction detection signal is not required, and the first instruction decoder 15 can generate a user-defined instruction detection signal. No circuit is required.

[0107]

According to the present invention, the first, second, third, fourth, fifth, sixth, seventh or eighth invention (claims 1, 2, 3,
According to the processing device described in 4, 5, 6, 7 or 8, the first instruction decoder for decoding the non-user-defined instruction is provided by providing the second instruction decoder for decoding the user-defined instruction in the user-specific circuit. Can make the contents of the user-defined instruction unrelated at all. Therefore, even if the contents of the user-defined instruction are different for each user, there is no need to redesign the first instruction decoder. By incorporating in advance a set of instructions that can be used as a user-defined instruction, the user can use it as a user-defined instruction without changing a processor core that is optimally designed by full custom design. You can define your own instructions for the available instructions.

According to the ninth aspect of the present invention, the same effect as that of the seventh aspect can be obtained, and an interrupt suppressing circuit is provided. Even when an interrupt occurs while a user-defined instruction of a plurality of words is being fetched, this can be suppressed.

In the tenth or eleventh aspect of the present invention (the processing apparatus according to claim 10 or 11), the first
The same effect as that of the first invention can be obtained, and a circuit for outputting a user-defined instruction detection signal to the first instruction decoder is not required.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 illustrates a first embodiment of the present invention.
It is a figure showing the format of the non-user-defined instruction which consists of a word.

FIG. 3 shows a first embodiment used in the first embodiment of the present invention.
It is a figure showing the format of the user-defined instruction which consists of a word.

FIG. 4 shows 2 used in the first embodiment of the present invention.
It is a figure showing the format of the user-defined instruction which consists of a word.

FIG. 5 shows 3 used in the first embodiment of the present invention.
It is a figure showing the format of the user-defined instruction which consists of a word.

FIG. 6 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 7 shows a first embodiment used in the second embodiment of the present invention.
It is a figure showing the format of the user-defined instruction which consists of a word.

FIG. 8 illustrates a second embodiment of the present invention.
It is a figure showing the format of the user-defined instruction which consists of a word.

FIG. 9 shows 3 used in the second embodiment of the present invention.
It is a figure showing the format of the user-defined instruction which consists of a word.

FIG. 10 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 11 is a block diagram showing a main part of an example of a conventional system ASIC.

[Explanation of symbols]

 7 Processor core 8 User-specific circuit 9 Bus 10 First instruction decoder 11 Non-user-defined instruction execution unit 12 Second instruction decoder 13 User-defined instruction execution unit

Claims (11)

[Claims] 1. A processing apparatus comprising: a processor core having a non-user-defined instruction execution unit for executing a non-user-defined instruction; and a user-specific circuit having a user-defined instruction execution unit for executing a user-defined instruction. A first instruction decoder for decoding a non-user-defined instruction, and a second instruction decoder for decoding the user-defined instruction in the user-specific circuit. 2. The first instruction decoder and the second instruction decoder are supplied with the same instruction in parallel via a common bus, and the first instruction decoder has a fetched instruction as a user-defined instruction. The second instruction decoder is configured to recognize an instruction identified as a user-defined instruction by the first instruction decoder as a user-defined instruction. Claim 1
The processing device according to the above. 3. A user-defined instruction comprising one word,
The one-word user-defined instruction has an instruction field in which an instruction code indicating a user-defined instruction and a word length is written, and an instruction field in which an instruction code indicating a type of the instruction is written. When the decoder fetches the one-word user-defined instruction, the decoder recognizes that the fetched instruction is a user-defined instruction and recognizes the word length from the user-defined instruction and the instruction code indicating the word length. A detection signal is output to the second instruction decoder, and thereafter, fetching of the next instruction is stopped until a user-defined instruction execution completion signal is received from the second instruction decoder. In the case where the definition instruction is taken in, when the user-defined instruction detection signal is received from the first instruction decoder, Recognizes the fetched instruction as a user-defined instruction, recognizes the word length of the fetched user-defined instruction from the user-defined instruction and the instruction code indicating the word length, and the user-defined instruction execution unit completes execution of the user-defined instruction. If you do
3. The processing device according to claim 2, wherein the processor is configured to output a user-defined instruction execution completion signal to the first instruction decoder. 4. A user-defined instruction comprising a plurality of words, wherein the user-defined instruction comprising a plurality of words includes, in a first word, an instruction field in which a user-defined instruction and an instruction code indicating a word length are written; The first instruction decoder indicates a user-defined instruction and a word length when the first word of a user-defined instruction consisting of a plurality of words is fetched. Recognize that the fetched instruction is a user-defined instruction and the word length from the instruction code,
Each time the second and subsequent words are fetched sequentially, a user-defined instruction detection signal is output to the second instruction decoder each time the first and subsequent words are fetched, and the second word is fetched after the last word is fetched. The second instruction decoder stops fetching the next instruction until receiving the user-defined instruction execution completion signal from the instruction decoder. The second instruction decoder, when fetching the first word of the user-defined instruction consisting of a plurality of words, When a user-defined instruction detection signal is received from the decoder, the fetched instruction is recognized as a user-defined instruction, and the word length of the fetched user-defined instruction is recognized from the user-defined instruction and the instruction code indicating the word length. Each time a second or later user-defined instruction detection signal is received from the first instruction decoder, Processing the words fetched in parallel as words of a user-defined instruction, and outputting the user-defined instruction execution completion signal to the first instruction decoder when the user-defined instruction execution unit completes execution of the user-defined instruction. 4. The processing apparatus according to claim 3, wherein the processing apparatus is configured to perform the processing. 5. An instruction code indicating a user-defined instruction is different for each user-defined instruction having a different word length, and is also used as an instruction code indicating a word length. 5. The processing apparatus according to 4. 6. It has a user-defined instruction consisting of one word,
The one-word user-defined instruction has an instruction field in which an instruction code indicating a user-defined instruction is entered, and an instruction field in which an instruction code indicating a word length and an instruction type is entered. When the first instruction decoder captures the user-defined instruction including the one word, the first instruction decoder recognizes that the captured instruction is a user-defined instruction, and outputs a user-defined instruction detection signal to the second instruction decoder. Stop receiving the next instruction until receiving the user-defined instruction execution completion signal from the second instruction decoder, and, when receiving the user-defined instruction detection signal from the first instruction decoder, the second instruction decoder Recognizes the word fetched in parallel with the instruction decoder as a user-defined instruction, and determines whether the instruction code indicates the word length and instruction type When the user-defined command execution unit completes the execution of the user-defined command, the user-defined command execution completion signal is sent to the first command. 3. The processing device according to claim 2, wherein the processing device is configured to output to a decoder. 7. A user-defined instruction comprising a plurality of words, wherein the user-defined instruction comprising a plurality of words includes, in a first word, an instruction field in which an instruction code indicating a user-defined instruction is written; An instruction field in which an instruction code indicating a length and an instruction type is written, and an instruction field in which an instruction code indicating a user-defined instruction is written in each of the second and subsequent words, Each time the first instruction decoder takes in each word of the user-defined instruction consisting of the plurality of words, the first instruction decoder recognizes that the instruction is a user-defined instruction from an instruction code indicating that the instruction is a user-defined instruction, and generates a user-defined instruction detection signal. The second
Output to an instruction decoder, and each time a user-defined instruction detection signal is output to the second instruction decoder, stopping fetching of the next word until receiving a user-defined instruction execution completion signal from the second instruction decoder; A second instruction decoder configured to output 1 from the first instruction decoder;
When the second user-defined instruction detection signal is received, the word length of the fetched user-defined instruction is recognized from the instruction code indicating the word length and the type of the instruction, and the fetch of the last word from the first instruction decoder is performed. Until the user-defined instruction detection signal is received, every time the user-defined instruction detection signal is received, the user-defined instruction execution completion signal is output to the second instruction decoder even though the user-defined instruction has not been executed, and , Each time a user-defined instruction detection signal is received from the first instruction decoder,
A word fetched in parallel with the instruction decoder is recognized and processed as a user-defined instruction, and when the user-defined instruction execution unit completes execution of the user-defined instruction, the user-defined instruction execution completion signal is sent to the first instruction decoder. 7. The apparatus of claim 6, wherein
The processing device according to the above. 8. An instruction code indicating a user-defined instruction is one type of instruction code regardless of a word length.
8. The processing device according to claim 7, wherein the instruction code indicating the word length can also serve as an instruction code indicating a type of the instruction. 9. An interrupt suppressing circuit for suppressing input of an interrupt signal while an interrupt suppressing signal is supplied, wherein the second instruction decoder fetches a first word of a user-defined instruction composed of a plurality of words. 8. The processing apparatus according to claim 7, wherein in the case, the interruption suppression signal is supplied to the interruption suppression circuit until the last word is fetched. 10. The first instruction decoder and the second instruction decoder are supplied with the same instruction in parallel via a common bus, and when the second instruction decoder fetches a user-defined instruction, 2. The processing apparatus according to claim 1, wherein the processor is configured to recognize the fetched instruction as a user-defined instruction from an instruction code indicating that the instruction is a user-defined instruction, regardless of the first instruction decoder. 11. The second instruction decoder, when the user-defined instruction execution unit completes execution of a user-defined instruction,
A first instruction decoder outputs a user-defined instruction execution completion signal to a first instruction decoder. When the first instruction decoder receives a user-defined instruction, the first instruction decoder stops capturing of a next instruction until receiving the user-defined instruction execution completion signal. The processing apparatus according to claim 10, wherein the processing apparatus is configured.