JP2009163328A - Information processor and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor including a reconfigurable circuit and an information processing method for executing specific processing at high speed. <P>SOLUTION: A storage part 12a stores first information showing a circuit related with specific processing and second information showing whether or not a processing time by the circuit shown by the first information depends on data. When recognizing a specific call, a first processor 11 refers to the first information, and judges whether or not the call is executable by a reconfigurable device 12, and when it is judged that the call is not executable, the first processor 11 executes processing, and outputs the processing result, and when judging that the call is executable by the reconfigurable device 12, the first processor 11 refers to the second information, and when it is judged that the processing time does not depend on the data, the reconfigurable device 12 executes the processing, and outputs the result, and when it is judged that the processing time depends on the data, the first processor 11 and the reconfigurable device 12 are made to simultaneously execute the processing, and the result of the processing which has been completed first is output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing apparatus including, for example, a processor and a reconfigurable circuit whose circuit configuration can be changed, and a control method thereof.

  Data processing devices have been developed that use a reconfigurable logic circuit to speed up arithmetic processing. As a conventional data processing device using a reconfigurable logic circuit, for example, a technology has been developed in which reconfigurable hardware (hereinafter abbreviated as HW) is reconfigured in advance so as to realize processing that is desired to be accelerated. (See, for example, Patent Document 1). However, this data processing apparatus is a method in which a reconfigurable HW is made available only when it is desired to use it, and the reconfigurable HW cannot be changed dynamically. Further, when there are a plurality of functions to be accelerated, it is necessary to prepare a plurality of reconfigurable HWs, which increases the circuit scale.

  In addition, a data processing apparatus capable of dynamically reconfiguring the HW has been developed (see, for example, Patent Document 2). In this data processing apparatus, when a specific instruction is executed, the CPU determines which is faster, in the case where the process is executed in the HW after the HW is reconfigured or in the case where all processes are executed by the CPU. . As a result, if it is determined that the processing in the HW is faster after the HW is reconfigured, the CPU outputs an instruction to reconfigure the HW, and the CPU performs the data processing and the HW reconfiguration in parallel. And execute. After completing the reconfiguration of the HW, the CPU passes the intermediate result of the processing to the HW, prepares for the execution of the processing, and causes the HW to execute the processing. While the CPU causes the HW to execute a process, it is possible to execute another process in parallel.

  In the case of this data processing apparatus, CPU processing and HW processing can be executed in parallel, and the time required for HW reconfiguration can be suppressed from causing a delay in the time required for the entire processing.

However, in this data processing apparatus, if it is not easy to determine which is faster when executing processing at the HW after reconfiguration of the HW or when executing all processing at the CPU, this determination is made. During this period, processing by the CPU does not proceed. In particular, when the time required for processing depends on data, it is difficult to determine which processing is faster before execution, resulting in further processing delay.
Japanese Patent No. 3340343 Japanese Patent No. 3723775

  An object of the present invention is to provide an information processing apparatus including a reconfigurable circuit and capable of performing high-speed processing when executing specific processing, and a control method thereof.

  An aspect of the information processing apparatus according to the present invention includes a first processor, a reconfigurable device connected to the first processor and capable of reconfiguring a circuit configuration, a specific process provided in the reconfigurable device And a storage unit that stores second information indicating whether or not the processing time of the specific processing by the circuit indicated by the first information depends on data. When the first processor recognizes the call of the specific process, the first processor refers to the first information stored in the storage unit and determines whether the call can be executed by the reconfigurable device. If it is determined that the call cannot be executed, the first processor executes processing, outputs a processing result, and the reconfigurable device outputs the processing result. The second information stored in the storage unit is referred to, and if it is determined not to depend on the data, the specific process is executed in the reconfigurable device and the result is determined. And the first processor and the reconfigurable device are processed at the same time, and the result of the earlier processing is output.

  According to the aspect of the control method of the information processing apparatus of the present invention, when the first processor recognizes the call of the specific process, the first processor shows a circuit configuration related to the specific process stored in the storage unit of the reconfigurable device. 1 is referred to to determine whether the call can be executed by the reconfigurable device, and if it is determined that the call cannot be executed, the first processor executes the processing and the processing result is obtained. If the output is determined and the call can be executed by the reconfigurable device, whether the processing time of the specific processing by the circuit indicated by the first information stored in the storage unit depends on the data If the data does not depend on the data, the reconfigurable device executes the specific process and outputs the result. Depend on the data is to simultaneously process the reconfigurable device and the first processor, characterized in that the fast processing and outputs the result of the person who has finished.

  According to the present invention, it is possible to provide an information processing apparatus including a reconfigurable circuit and capable of performing high-speed processing when executing specific processing, and a control method thereof.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment)
First, the configuration of the present embodiment will be schematically described with reference to FIG.

  The first processor 11 includes, for example, an ALU (arithmetic and logic unit) 11a. The first processor 11 is connected to the reconfigurable device 12. The first processor 11 is connected to the bus 15 via an interface (hereinafter abbreviated as I / F) 14, and the reconfigurable device 12 is connected to the bus 15 via an I / F 16. The reconfigurable device 12 is provided with a status register 12a as a storage unit, for example. The status register 12a stores a configuration ID as identification information indicating the circuit configuration in the reconfigurable device 12, and a flag (FLG) indicating whether the processing time of the set circuit depends on the data. ing.

  The second processor 13, the main memory 17, and a DMAC (Direct Memory Access Controller) 18 are connected to the bus 15, and the DMAC 18 receives an instruction from the second processor 13 and controls the operation of the main memory 17.

  The first local memory 19 is connected to the first processor 11 and is connected to the bus 15 via the I / F 14. The second local memory 20 is connected to the first processor 11 and the reconfigurable device 12, and is connected to the bus 15 via the I / F 14. The first local memory 19 stores, for example, a program and data of the first processor 11. The second local memory 20 stores, for example, data shared by the first processor 11 and the reconfigurable device 12.

  For example, a DSP (Digital Signal Processor) 21 and a VLIW (Very Long Instruction Word) coprocessor 22 are respectively connected to the second local memory 20.

  An SDRAM (Synchronous Dynamic Random Access Memory) 23 is connected to the bus 15 via an SDRAMC (Synchronous Dynamic Random Access Memory Controller) 24. The peripheral devices 25 and 26 are connected to the bus 27. The peripheral devices 25 and 26 are, for example, a serial I / F or a UART (Universal asynchronous receiver transmitter). The bus 27 and the bus 15 are connected to the bus bridge 28.

  The first processor 11 is, for example, a media processing processor, and can execute a specific process, for example, a function process, by software (hereinafter abbreviated as SW). The function processing is a set of a plurality of instructions, for example, a function processing subroutine. When the function processing is called, the first processor 11 refers to the flag and the configuration ID from the status register 12a. The first processor 11 determines what the circuit configuration related to the function processing set on the reconfigurable device 12 is based on the configuration ID. When the function processing is executed, either the reconfigurable device 12 or the SW is executed simultaneously with the configuration ID and the flag.

  When function processing is executed using at least one of the first processor 11 and the reconfigurable device 12, data necessary for processing is transferred from the main memory 17 to the second local memory 20 via the bus 15 and the I / F 14. Forwarded to At least one of the first processor 11 and the reconfigurable device 12 reads data from the second local memory 20 and executes function processing. When the reconfigurable device 12 is executing processing, the first processor 11 receives the interrupt request (Interrupt Request: hereinafter abbreviated as IRQ) from the reconfigurable device 12 and reconfigurable. The processing result is collected from the device 12.

  The reconfigurable device 12 is a circuit whose internal configuration can be changed based on, for example, data given from the outside. The reconfigurable device 12 reconfigures a circuit related to function processing, for example, in accordance with a reconfiguration command from the second processor 13. The reconfigurable device 12 stores a configuration ID, which is first information indicating the set circuit, in the status register 12a. If the time required for function processing by a circuit indicated by a certain configuration ID depends on the data, a flag as second information is set in the status register 12a. When the reconfigurable device 12 executes and completes the function processing, the IRQ is output to the first processor 11.

  The second processor 13 is, for example, an overall control CPU that controls the entire circuit of the present invention and also serves as a reconfiguration process. The second processor 13 monitors the calling of the configuration ID to the status register 12a by the first processor 11. When the configuration ID is called by the first processor 11 and does not match the configuration ID set in the status register 12a, and the number of times of the mismatch continues over a predetermined value, for example, several times, the second processor 13 Sets a circuit based on the configuration ID in which the number of mismatches is equal to or greater than a specified value in the reconfigurable device 12. Each time the reconfigurable device 12 is reconfigured, the second processor 13 rewrites the configuration ID and flag setting of the status register 12a. The second processor 13 sets a circuit that is considered to be used most frequently in the reconfigurable device 12 in advance when the system is started.

  The main memory 17 stores, for example, configuration data used for reconfiguration of the reconfigurable device 12.

  Next, the present embodiment will be specifically described with reference to FIGS. 1, 2, and 3, focusing on the operation of the first processor 11.

  When the first processor 11 recognizes a function call (for example, a subroutine call for executing a function process) as a specific process (S101), the first processor 11 stores a status register 12a provided in the reconfigurable device 12 in the status register 12a. The set configuration ID is referred to (S102). Based on the referenced configuration ID, it is determined whether or not the circuit configuration set in the reconfigurable device 12 can execute the function (S103).

  When the circuit configuration can execute the function, the first processor 11 determines from the status register 12a whether the time required for the function processing depends on the data, that is, whether the flag is set (S104). .

  When the flag is not set, the first processor 11 causes the reconfigurable device 12 to execute the function execution process (S105).

  When the process is completed, the reconfigurable device 12 outputs an IRQ to the first processor 11 (S106). When receiving the IRQ from the reconfigurable device 12, the first processor 11 collects and outputs the processing result from the reconfigurable device 12 (S107).

  If it is determined in step S104 that the flag is set, function processing is executed by the reconfigurable device 12 and the SW of the first processor 11 (S108). When the IRQ is output from the reconfigurable device 12 to the first processor 11 (S109), the first processor 11 stops the SW process (S110), collects the result from the reconfigurable device 12, and outputs the result. (S111).

  On the other hand, when the SW processing is completed before the IRQ is output from the reconfigurable device 12 in a state where the function processing is executed by the reconfigurable device 12 and the SW (S112), the first processor 11 The function process of the reconfigurable device 12 is stopped (S113), and the result of the SW process is output (S114).

  By the way, the second processor 13 monitors the access status of the first processor 11 to the status register 12a. If the second processor 13 determines in step S103 that the configuration ID called by the first processor 11 does not match the configuration ID stored in the status register 12a, the number of mismatches is a specified value as shown in FIG. It is determined whether or not this is the case (S201). If the number of mismatches does not reach the specified value, the first processor 11 executes function processing with SW and outputs the result (S202). If the number of mismatches continues for a specified number of times (specified value) or more, for example, the second processor 13 determines that the probability that the same configuration ID is called is high, and reconfigures the configuration data corresponding to this configuration ID from the main memory 17. Then, the setting of the circuit in the reconfigurable device 12 is started (S203). The first processor 11 executes function processing by SW and outputs the result (S202). During the process execution by SW, the reconfigurable device 12 reconfigures the circuit based on the supplied configuration data (S204). The second processor 13 sets a configuration ID and a flag in the status register 12a based on the reconfigured circuit (S205).

  According to the above embodiment, the reconfigurable device 12 includes the status register 12a, and the status register 12a relates to the configuration ID indicating the circuit configuration related to the function processing set in the reconfigurable device 12, and to the function processing. A flag indicating that the processing time of the circuit configuration depends on the data is stored. When the first processor 11 recognizes the function processing call, the first processor 11 determines the configuration ID and the flag, and switches the processing of the first processor 11 and the reconfigurable device 12. Therefore, it is not necessary to determine the processing time of the reconfigurable device 12 and the SW processing time by the first processor 11 or to determine whether or not the reconfigurable device 12 should be reconfigured. Only by this determination, either the first processor 11 or the reconfigurable device 12 can execute processing. In addition, when processing is executed by both the first processor 11 and the reconfigurable device 12, the processing result that has been completed earlier is used. For this reason, the processing speed can be increased.

  Further, whether or not the reconfigurable device 12 should be reconfigured and the reconfiguration command are issued by the second processor 13. For this reason, the first processor 11 does not need to spend time for reconfiguring the reconfigurable device 12. Therefore, it is possible to prevent a decrease in the performance of the entire system.

  Further, the second processor 13 monitors data between the first processor 11 and the reconfigurable device 12, and the config ID called by the first processor 11 and the config set in the status register 12a. If the IDs do not match and the same configuration ID is called multiple times, the reconfigurable device 12 is reconfigured. For this reason, when the same function call is made a plurality of times, the processing is executed using the reconfigurable device 12 reconfigured corresponding to the configuration ID, so that the processing can be speeded up. .

Further, a complicated communication mechanism is not provided between the reconfigurable device 12, the second processor 13, and the first processor 11. For this reason, it is possible to simplify the system configuration, and it is possible to construct a system with excellent extensibility and few bugs.
Next, a modification of the above embodiment will be described. In the modification, the second processor 13 stores the order (pattern) of the configuration IDs that the first processor 11 has called so far, that is, the order of the functions executed so far in the main memory 17, for example. The pattern of the called config ID is detected by pattern matching or the like. The second processor 13 predicts the next config ID to be called by matching. For example, when the first processor 11 calls the configuration IDs A, B, and C in the order A, B, and C, and does not match the configuration ID set in the status register 12a, for example, the configuration ID A is set. Is called, the second processor 13 estimates that the next is B while processing A in the SW, and instructs the reconfigurable device 12 to reconfigure B during the processing of A. .

  According to the modification of the above embodiment, the second processor 13 stores the pattern of the function executed so far, and then executes the function by matching the executed function with the stored pattern. And a reconfiguration command for implementing the function in accordance with the prediction is output to the reconfigurable device 12. Thereby, it becomes possible to perform reconfiguration of the reconfigurable device 12 efficiently, and it is possible to efficiently utilize the reconfigurable device 12 in function processing.

  In the above embodiment, function processing has been described. However, the present embodiment is not limited to this. For example, the present embodiment can also be applied to a case where a specific instruction is processed.

The block diagram which shows the information processing apparatus of embodiment of this invention. 2 is a flowchart showing the operation of the information processing apparatus shown in FIG. FIG. 3 is a flowchart showing processing subsequent to the flowchart shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... 1st processor, 12 ... Reconfigurable device 12a ... Status register, 13 ... 2nd processor.

Claims (5)

A first processor;
A reconfigurable device connected to the first processor and capable of reconfiguring a circuit configuration;
First information that is provided in the reconfigurable device and indicates a circuit configuration related to specific processing, and whether or not a processing time of the specific processing by the circuit indicated by the first information depends on data. A storage unit for storing second information to be displayed,
When the first processor recognizes the call of the specific process, the first processor refers to the first information stored in the storage unit, determines whether the call can be executed by the reconfigurable device, and When it is determined that the call cannot be executed, the first processor executes processing and outputs a processing result. When it is determined that the call can be executed by the reconfigurable device, the call is stored in the storage unit. The second information is referred to, and when it is determined that it does not depend on data, the specific process is executed by the reconfigurable device and a result is output. An information processing apparatus that simultaneously processes one processor and the reconfigurable device and outputs the result of the earlier completion of processing . Further comprising: a first processor connected to the reconfigurable device; and a second processor connected to the reconfigurable device.
The second processor configures a circuit configuration based on the first information in the reconfigurable device when the number of mismatches with respect to the first information called by the first processor is equal to or greater than a predetermined value. The information processing apparatus according to claim 1.   The second processor stores a calling order of the first information called by the first processor, and collates the stored order with the first information called by the first processor. The information processing apparatus according to claim 2, wherein an order of the first information to be called next is predicted, and reconfiguration according to the predicted order is instructed to the reconfigurable device. When the first processor recognizes the call of the specific process, the first processor refers to the first information indicating the circuit configuration related to the specific process stored in the storage unit of the reconfigurable device, and stores the call to the reconfigurable device. To determine if the call can be executed,
If it is determined that the call cannot be executed, the first processor executes processing and outputs a processing result;
If it is determined that the call can be executed by the reconfigurable device, it indicates whether the processing time of the specific processing by the circuit indicated by the first information stored in the storage unit depends on data Referring to the second information, if it does not depend on the data, execute the specific processing in the reconfigurable device and output the result,
A method for controlling an information processing apparatus, characterized in that when it depends on data, the first processor and the reconfigurable device are processed at the same time, and the result of the earlier processing is output. Further comprising: a first processor connected to the reconfigurable device; and a second processor connected to the reconfigurable device.
The second processor configures a circuit configuration based on the first information in the reconfigurable device when the number of rejects for the first information called by the first processor is equal to or greater than a predetermined value. The method of controlling an information processing apparatus according to claim 4.

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