JPH1139140A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the comparison of a pair of data and the selection of two resultant pairs of the data. SOLUTION: From four registers specified by a comparison and selection instruction inside a register circuit 2, a pair of data (a) and (b) are supplied to an arithmetic and logic circuit (ALU) 3 and a selection circuit 4, and the other pair of data (e) and (f) are supplied to a selection circuit 5. In the ALU 3, the size of the data (a) and (b) is compared. The selection circuits 4 and 5 select one, smaller one for instance, of the data (a) and (b) corresponding to the compared result, while the selection circuit 5 selects the smaller one of the data (e) and (f). Two data (c) and (g) selected in the selection circuits 4 and 5 are written in the predetermined pair of the registers inside the register circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a processor controlled by a program such as a microcomputer or a digital signal processor.

[0002]

2. Description of the Related Art In a conventional microcomputer or a processor such as a digital signal processor, when performing comparison and selection processing, subtraction for comparison and branch processing based on the subtraction are required. Therefore, in order to eliminate the branching process, the speed of the comparison and selection process has been increased as described in JP-A-58-205253. Further, due to the recent development of digital communication, there is a process called maximum likelihood decoding process (also referred to as Viterbi process) among processes performed by a processor. The maximum likelihood decoding process refers to performing a decoding process by calculating an error between two types of expected data to be received and actually received data, and sequentially selecting a smaller error. Things. Therefore, in the maximum likelihood decoding process, the comparison and selection process is performed a plurality of times. In order to perform the comparison and selection processing at high speed, Texas Instruments “TMS320C54x”
Section 2.5.5 of User's Guide ”(P2-2
4, 25, 26).

[0003]

As one of digital signal processing by a program using a processor, there is a voice coding processing. CEL is included in this audio coding system.
There is a processing method called a P method, and this method is widely used in digital mobile phones. In the CELP method, many comparison and selection processes are performed in selecting a sound source codebook and the like. Here, in the selection of the sound source codebook, a restored speech is generated for each sound source codebook, and the one with the smallest error between this and the input speech is selected. In this process, the error between the restored voice and the input voice is calculated first, compared with the previously obtained error which was the smallest, and if the newly calculated error is smaller, the error is minimized. The error is left as an error, and the codebook number used to determine the error is stored. That is, in the search for the sound source codebook, two of the speech error and the codebook number are selected by comparing the speech errors.
I mean. Two selection processes are performed based on one comparison result. On the other hand, in the above-mentioned conventional technology, it is necessary to execute by a plurality of instructions. For example, "TMS320C54
Even when the function described in “x User's Guide” is used, the following processing is required.

1) The larger of A and B is stored in B.

[0005] 2) If Condition code C
== 1 then branch to 4) 3) Copy AR1 to AR2 (save codebook number) 4) Next processing As described above, in the above-mentioned conventional example, two values are compared and one of them is selected. Although the comparison and selection processing can be performed, the number of processing steps is increased in the comparison and selection processing in which selection is performed twice for one comparison as in a codebook search. For this reason, an increase in the number of processing steps increases the operating speed of the processor and increases power consumption, and an increase in code size increases a required memory amount.

An object of the present invention is to provide a processor which can execute a plurality of selection processes based on a single comparison result at high speed.

[0007]

In order to achieve the above object, a processor according to the present invention reads two pairs of data from a register circuit in response to a comparison / selection instruction, and performs comparison between the two pairs of data. And selecting one of the pair of data and one of the other pair of data based on the comparison result. That is, a processor according to the present invention includes a register circuit including a plurality of registers that can be specified by an instruction, an arithmetic unit capable of comparing a pair of data, and one of the pair of data according to a comparison result by the arithmetic unit. There is a first selection circuit for selecting, and a second selection circuit for selecting one of the other pair of data according to the result of comparison by the arithmetic unit.

The register circuit supplies the pair of data from the pair of registers to the arithmetic unit and the first selection circuit in response to the comparison / selection command. The other pair of data is supplied from another pair of registers in the register to the second selection circuit, and the first and second data selected by the first and second selection circuits are selected.
A circuit for storing the second selection result data in two different registers among the plurality of registers;

According to the present invention, a processor which divides each data in a pair of registers designated by one instruction into different parts and performs the same operation on each part in parallel (hereinafter referred to as a SIMD type processor). Also applicable to

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a processor according to the present invention will be described in more detail with reference to some embodiments shown in the drawings. In the following, the same reference numerals represent the same or similar ones. Also,
In the second and subsequent embodiments, differences from the first embodiment will be mainly described.

<Embodiment 1> An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a processor to which the present invention is applied. This processor is formed on one large-scale integrated circuit (LSI). The processor decodes an instruction code and generates a control signal for each block, an instruction decoding unit 1, a register circuit 2 for storing a value used for operation, an operation result, and the like, and an arithmetic and logic operation circuit for performing addition and subtraction. (ALU) 3, selection circuits 4 and 5, memory 8 and bus 7. Bus 7 is used to transfer instructions and data between memory 8 and instruction decode unit 1 and register circuit 2.

FIG. 2 shows the configuration of the selection circuit 4. The selection circuit 4 includes a control signal group 104, a decoding circuit 41 for generating selection signals 901 and 902 based on the N flag 302, and two input data 20 based on the selection signals 402 and 403.
1 and 202, and is configured by a selector 42 that selects an output 401. The selector 42 selects the selection signal 402
Is 1, the input data 201 is set to the output 401 and 4
If 03 is 1, the input data 202 is set as the output 401.

FIG. 3 shows the configuration of the decoding circuit 41. The decoding circuit 41 has four AND circuits 43, 44, 4
5 and 46 and two OR circuits 47 and 48. The control signal group 104 includes two signals 112 and 12
Consists of two. The signal 112 sets the selection signal 402 to 1 when the N flag 302 is 1, and sets the selection signal 403 to 1 when the N flag 302 is 0. Conversely, the signal 122 sets the selection signal 402 to 1 when the N flag 302 is 0, and sets the selection signal 403 to 1 when the N flag 302 is 1. The configuration of the selection circuit 5 is the same as that of the selection circuit 4. At this time, it is obvious that the decoding circuit 41 can be shared by the selection circuits 4 and 5.

FIG. 4 shows the structure of the register circuit 2. The data transfer path is connected to the bus 7 via the bus 210 and the interface circuit 21, and is used to store the data held in these registers in the memory 8. These registers are further connected to the bus 7 via the bus 220 and the interface circuit 22. This data transfer path is used to store the data held in the memory 8 in these registers. The interface circuits 21 and 22 output signals 211 and 2 included in the control signal 101.
21 respectively.

These registers are further connected to buses 201 to 204. Each of the registers has a built-in transfer control circuit (not shown). The transfer control circuit includes a control signal 231 and a control signal 231 included in the control signal 101. 241, 251,
261, 271 and 281 from the bus 201
04 is instructed to transfer data to
The data held by the register is transmitted to the bus.
These registers are further connected to the bus 301,
Used for storing the operation result by LU3. Register 2
7 is further connected to the bus 501 and is used for storing data selected by the selection circuit 5. Register 2
Reference numeral 8 is connected to the bus 401 and is used for storing data selected by the selection circuit 4. Each of these registers 21 to 28 has a built-in transfer control circuit (not shown).
When one of 2, 242, 252, 262, 272, and 282 instructs to take in data on any of the buses 301, 401, and 501, the data on that bus is taken into the register. As described above, in the present embodiment, the two registers holding the data selected by the selection circuits 4 and 5 are fixed to the registers 28 and 27.
As a result, the number of registers specified by the comparison / selection instruction described later is reduced, thereby preventing the instruction length from increasing.

The operation of the present processor is as follows. First, the instruction decode unit 1 decodes the code of the instruction read from the memory 8 via the bus 7, and outputs the control signal 102 to the register circuit 2, the control signal 103 to the ALU 3, and the selection circuits 4 and 5. Is generated and output. The register circuit 2 stores the input data 2 of the ALU 3
01, 202, and input data 203 of the selection circuit 5,
204, the control signal 102 from the internal register
And outputs the value stored in the register selected.
The ALU 3 performs an operation using the input data 201 and 202 according to the control signal 103, and outputs an operation result 301 to the register circuit 2. The register circuit 2 outputs the operation result 301 of the ALU 3 or the output of the selection circuits 4 and 5 to the control signal 1.
02, each is stored in a register in the register circuit 2. For example, in the case of an instruction for performing a normal operation by ALU3, the data held in registers a and b
And the operation result of the data is stored in the register c.
Is stored in

The comparison / selection instruction newly provided in this embodiment is executed as follows. As shown in FIG. 1, this instruction includes a pair of registers for holding two data a and b to be supplied to the ALU 3 and the selection circuit 4, and a pair of registers for holding data e and f to be supplied to the selection circuit 5. And a pair of registers. This instruction does not specify a register to hold the data d selected by the selection circuit 4 among the data a and b and a register to hold the data selected by the selection circuit 5 among the data e and f. These data are determined to be written into the registers 28 and 27 (FIG. 4) under the control of the instruction decoding unit 1, respectively.

The execution of this instruction is executed under the control of the instruction decoding unit 1 as follows. First, according to the control signal 101, data a and b are converted into data 201 and 202 from the two registers designated by this instruction as data 201 and 202, respectively.
And data e and f from the other two registers specified by this instruction are supplied to the selection circuit 5 as data 203,
Read as 204. AL by control signal 103
In U3, the input data 202 is subtracted from the input data 201. The selection circuit 4 includes a control signal group 104 and an N flag 302 indicating that the operation result 301 has become a negative value.
, One of the input data 201 and 202 of the ALU 3 is selected as an output 401. Further selection circuit 5
, Using the control signal group 104 and the N flag 302 output by the ALU 3 as in the selection circuit 4,
And 204 are selected as output 501.

The comparison / selection instruction used in the present embodiment includes a first comparison / selection instruction for selecting the smaller one of the two data, and a second comparison / selection instruction for selecting the larger one of the two data. There is. When the two data have the same value, any one of the comparison / selection commands selects a predetermined one. Alternatively, none of the selection commands and any data can be selected. When the comparison / selection instruction decoded by the instruction decoding unit 1 is the first comparison / selection instruction, the instruction decoding unit 1 sets the signal 112 in the control signal group 104 to 1, and the comparison / selection instruction decoded by the instruction decoding unit 1 Is the second comparison / selection instruction, the instruction decoding unit 1 is configured to set the signal 122 to 1. In the selection circuit 5, the data 2
If 01 is selected, data 203 is selected, and if data 202 is selected in the selection circuit 4, data 204 is selected. The data d and g selected by the selection circuits 4 and 5 are written into two predetermined registers 28 and 27 (FIG. 4). Thus, the comparison and selection process of comparing the pair of data a and b, selecting one of them, and selecting one of the other pair of data e and f can be executed at high speed with one instruction.

<Embodiment 2> In the present embodiment, a comparison / selection instruction for specifying a register for storing data selected by the selection circuits 4 and 5 is used. That is, as shown in FIG. 5, in this instruction, two registers for holding a pair of data a and b to be supplied to the ALU 3 and another pair of data d and e to be supplied to the selection circuit 5 are held. 4 registers to be specified. Note that these instructions do not specify another register that holds the data selected by the selection circuits 4 and 5. These data are written into registers holding data b and e, respectively. The instruction length is shorter than when the registers for storing these data b and e are set to any other registers.

FIG. 6 shows the structure of the register circuit 2 for executing this instruction. As is clear from the comparison with FIG. 4, all the registers are connected to the buses 401 and 501, and both registers can take in the output data of the selection circuits 4 and 5. Note that, as the comparison / selection command, the first and second comparison / selection commands described in the first embodiment are also used in the present embodiment.

A description will be given of an execution mode of this instruction in a case where this instruction is applied to the comparison and selection processing of the codebook search in the CELP system audio encoding processing. First, among the registers in the register circuit 2, a register storing the smallest error (hereinafter referred to as register a) and a register storing the new error (hereinafter referred to as register b) are used. (Hereinafter referred to as register c) and a register (hereinafter referred to as register d) for storing a codebook number as an identification number corresponding to a new error when the new error is obtained. Registers are allocated. As a comparison / selection instruction, an instruction using the above-mentioned first comparison / selection instruction for designating these four registers and selecting the smaller of the two data is executed.

By executing this instruction, the value (new error) of the register b is set as data 201 and the register a
(Minimum error) as the data 202
The value of the register d (codebook number when a new error is obtained) is set as data 203 and the value of the register c (codebook number when the minimum error is obtained) is set as data 204. , Respectively. Thereafter, the control signal 103 causes the ALU
In 3, the data 202 is subtracted from the data 201, and the signal 112 in the control signal group 104 is set to 1. At this time, if the operation result 301 of the ALU 3 is a negative value, the selection circuit 4 outputs the data 201 as the output 401 and the selection circuit 5 outputs the data 203 as the output 501. Conversely, if the operation result 301 is a positive value, the selection circuit 4 outputs the data 202 as the output 401 and the selection circuit 5 outputs the data 204 as the output 50.
Let it be 1. Further, the output 401 of the selection circuit 4 is taken into the register a in which the smallest error has been stored, and the output 501 of the selection circuit 5 is stored in the codebook number register c when the smallest error has been obtained. Try to capture.

As a result, if the value of the register a is larger than the value of the register b, the new error stored in the register b is stored in the register a, and the register d is stored in the register c.
The codebook number at the time of finding the new error contained in the codebook is stored. Conversely, if the value of the register a is not larger than the value of the register b, both the registers a and c hold the previous values. With the above processing, two selection processings based on one comparison result can be executed by one instruction processing. In addition, two result data obtained by the comparison and selection processing can be stored in the register specified by this instruction.

By repeating this comparison and selection process for different error data, the minimum error among a large number of error data and the codebook number corresponding thereto can be obtained at high speed. It is needless to say that the identification number corresponding to the maximum value among a plurality of data can be detected by executing the second comparison / selection command in the same manner instead of the first comparison / selection command.

<Third Embodiment> In the present embodiment, an SIMD type processor to which the present invention is applied is provided. Here, the SIMD type processor refers to the upper data and the lower data of the lower half of each of the two registers specified by the instruction in the register circuit 2 as independent data. The same operation is performed in parallel on the data of
One register specified by this instruction stores data in the upper half and the lower half in parallel. Therefore, the instruction only specifies these three registers. Thus, SIMD
A type processor is a processor that executes the same operation on a plurality of register operands in parallel. In the following, it is assumed that each register is 32 bits.

In FIG. 7, the processor is an ALU 3a
Is supplied via lines 201a and 202a with two 16-bit data consisting of the upper half of each of the 32-bit data in the two registers specified by the instruction, and generates 16-bit data as a result of the operation. The signal is supplied to the register circuit 2 via the line 301a. The ALU 3b receives the lower 16 bits of data of these two registers from the lines 201b and 202b in exactly the same manner, and transmits the operation result to the line 3b.
01b to the register circuit 2. The selection circuits 4 and 5 are supplied with a pair of data supplied to the ALUs 3a and 3b, respectively. As in the first embodiment, the two selection circuits 4 and 5 are connected to the N flag 30 output by the ALU 3a.
2 and the selection process is performed according to the control signal group 104 in the same manner as in the first embodiment. In the present embodiment, the above-mentioned comparison / selection instruction specifies the first and second registers used for the operation and the third register for storing the result data of the comparison / selection processing, like the other instructions. First and second data to be compared are stored in the upper halves of the first and second registers in advance. These data are also a pair of data selected based on the result of the comparison. Another pair of data to be selected based on the result of the comparison is stored in the lower half of the first and second registers in advance.

As shown in FIG. 8, the upper 16 bits and lower 16 bits of the data read from the register designated by the instruction to the bus 201 are connected to lines 201a and 201, respectively.
b and supplied separately. The same applies to other data read to the bus 2010 from another register specified by the instruction. On the other hand, when an instruction requesting a normal operation in the ALU 3a, 3b is executed, the ALU 3a, 3b
Are supplied to all registers as upper data and lower data of the bus 3010, respectively. On the other hand, when the above-mentioned comparison / selection instruction is executed,
The outputs 401 and 501 of the selection circuits 4 and 5 are 302
It is transferred to all registers as upper data and lower data of 0.

As is clear from the above, even in the SIMD type processor, two selection processes based on one comparison can be executed in parallel. Moreover, the selection circuits 4, 5
The change of the structure of the register circuit 2 required for supplying the output of (1) to all the registers can be reduced.

<Modifications> It is needless to say that the present invention is not limited to the above embodiment, but can be realized by various modifications. For example, in each embodiment, a new comparator may be provided and used instead of the ALUs 3 and 3a.

[0031]

According to the present invention, the comparison of the values of a pair of data and the selection of one of the pair of data and one of the other pair of data depending on the result of the comparison are performed. 1
High-speed execution with instructions.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a processor according to the present invention.

FIG. 2 is a block diagram of a selection circuit used in the device of FIG.

FIG. 3 is a block diagram of a control circuit in a selection circuit used in the device of FIG. 2;

FIG. 4 is a block diagram of a register circuit used in the device of FIG. 1;

FIG. 5 is a schematic configuration diagram of another processor according to the present invention.

FIG. 6 is a block diagram of a register circuit used in the device of FIG. 5;

FIG. 7 is a schematic configuration diagram of still another processor according to the present invention.

FIG. 8 is a block diagram of a register circuit used in the device of FIG. 7;

Claims (7)

[Claims] A register circuit including a plurality of registers that can be specified by an instruction; an arithmetic unit capable of comparing a pair of data; and a second unit for selecting one of the pair of data according to a comparison result by the arithmetic unit. 1 selection circuit, and a second selection circuit that selects one of the other pair of data according to the comparison result by the arithmetic unit. The register circuit responds to a comparison / selection command, Among the plurality of registers, the pair of data is supplied from the pair of registers to the arithmetic unit and the first selection circuit, and the other pair of data is supplied from the other pair of registers in the plurality of registers. A second selection circuit supplies the first,
A processor having a circuit for storing first and second selection result data selected by a second selection circuit in two different registers among the plurality of registers. 2. The processor according to claim 1, wherein said pair of registers and said another pair of registers are registers specified by said comparison and selection instruction. 3. The processor according to claim 2, wherein said two registers for storing said first and second selection result data are predetermined registers. 4. The processor according to claim 2, wherein said two registers for storing said first and second selection result data are registers specified by said instruction. 5. The two registers for storing the first and second selection result data are the same as the register specified by the instruction as one of the pair of registers and the other pair of registers. Item 5. The processor according to item 4. 6. The processor according to claim 1, wherein said arithmetic unit is an arithmetic and logic unit capable of executing subtraction between said pair of data. 7. An arithmetic unit further comprising another arithmetic unit, wherein said arithmetic unit and said another arithmetic unit are capable of performing an arithmetic operation on a part of data that can be held in each of said plurality of registers. The register circuit supplies a first portion of each of a pair of registers specified by the operation instruction to the operation unit in response to the operation instruction, and Are supplied to the other operation unit, and a pair of operation result data supplied from the operation unit and the other operation unit are supplied to the first and second registers of another register designated by the operation instruction. 2, the register circuit responds to the comparison / selection command, and, in response to the comparison / selection command, the first part of each of a pair of registers specified by the command from the plurality of registers. 1
And a second portion of each of the pair of registers is supplied to the second selection circuit.
2. The processor according to claim 1, wherein a pair of data supplied from the second selection circuit is written to first and second portions of another register specified by the operation instruction.