JPS63174133A - Interruption controller - Google Patents

Abstract

PURPOSE:To enable an interruption processing routine at every I/O device to be performed even when plural interruption are allocated on the same level, by providing a ROM which outputs a vector number and a vectoring setting switch. CONSTITUTION:The interruption issued from the I/O devices 2 and 3 are processed commonly via an OR circuit 6, and after they are encoded at a priority order encoder 8 as the interruption lines of specified levels, they are supplied to a CPU1. The CPU1 outputs an interruption acknowledge signal to a level classified automatic/external vectoring setting switch 12 via a level classified interruption acknowledge detection circuit 11, and only the signal corresponding to a set level is selected, and is inputted to a ROM18 via an OR circuit 18. The ROM18 outputs a vector number obtained from an address information supplied via an address bus 9 and a code signal 17 to the CPU1 at the time of inputting an external vectoring enable signal 15. In such a way, it is possible to efficiently respond to the interruption requests for plural I/Os on the same level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an interrupt control device that responds to interrupt requests from external devices to a microprocessor.

[Prior art]

A vector number is fetched from an external device during the interrupt acknowledge cycle, and the start address of the interrupt routine is determined by reading it from a table in memory based on the fetched vector number, and then sent to the microprocessor (CPU). There is a method for performing interrupt operations.

However, I do not have the function to output vector numbers.
Interrupt control for 10 devices (hereinafter referred to as I10 devices including the interrupt generation circuit) is performed by this I10.
A single interrupt level was assigned to an interrupt from a device, and the start address of the interrupt routine was obtained through automatic vectoring without giving a vector number externally.

Therefore, when a plurality of interrupts are assigned to the same level, the interrupt routine has the disadvantage that it takes time and effort to search for the device that actually issued the interrupt from among the plurality of I10 devices.

〔the purpose〕

In view of the above points, the present invention makes it possible to start an interrupt processing routine for each I10 device that issues an interrupt of the same level even when a plurality of interrupts are assigned to the same level.

〔Example〕

The present invention will be explained below using preferred examples.

FIG. 1 shows an embodiment of the present invention, in which 1 is a CPU, 2 and 3 are I10 devices that do not have the function of generating vector numbers, and 4
and 5 are interrupt lines issued from I10 devices 2 and 3, respectively, 6 is an OR circuit, 7 is a common interrupt line obtained from the OR circuit, and 8 is a priority encoder.

9 is an address bus, lO is a function code that indicates the CPU operation, ll is a circuit that detects interrupt acknowledges for each level, and 12 is a switch that distinguishes automatic vectoring/external vectoring for each interrupt level, such as a connector.・It is a pin. 13 is an interrupt acknowledge line for the external vectoring level obtained from the circuit 12, 14 is an OR circuit, and 15 is an OR circuit 14.
16 is a latched encoder, 17 is a code signal that distinguishes the interrupt line 4.5 obtained from the latched encoder 16, and 18 is a vector number that has already been set for a given address input. 19 is a data bus.

Next, the operation of the above configuration will be explained.

Interrupts issued from I10 devices 2 and 3 are
The signal is shared through the R circuit 6, inputted to the priority encoder 8 as an interrupt line of a certain level, encoded, and then given to the CPUI. When interrupt processing becomes possible on the CPUI, it indicates through function code IO that an interrupt acknowledge cycle is in progress.
Furthermore, the lower several bits of address bus 9 are used to indicate the interrupt level currently set. The circuit 11 uses the function code 10 and address bus 9 to output interrupt acknowledge signals for each interrupt level. From these interrupt acknowledge signals, only those corresponding to the level set for external vector ringing are selected by a switch through the circuit 12, and are input to the OR circuit 14.

The OR circuit 14 supplies the ROM 18 with an external vectoring enable line 15 that is common to each side input level from the interrupt acknowledge line 13 for the level at which external vectoring is performed.

On the other hand, in response to interrupt lines 4 and 5 issued from I10 devices 2 and 3, latch encoder 16 outputs a code signal 17 that distinguishes the two from an external vector for the interrupt level to which interrupt lines 4 and 5 are assigned. It is given as part of the address information for the ROM 18 when the ring enable signal 15 is input. Note that this code signal 17 is latched at the start of the interrupt acknowledge cycle. Further, a lower bit line indicating the currently accepted interrupt level is inputted to the ROM 18 as address information at the same time as the code signal 17 from the address bus.

The ROM 18 outputs the vector number obtained from the address information to the data bus when the external vectoring enable signal 15 is input, and this vector number is fetched by the CPUI.

In this way, by providing the ROM 18 that generates vector numbers, it becomes possible to output the vector number corresponding to the I10 device even in response to an interrupt request from an I10 device that does not have a means to output a vector number. , the desired interrupt handling routine can be activated immediately. Furthermore, it becomes possible to distinguish between interrupts for a plurality of I10 devices arranged at the same level using hardware, thereby reducing the overhead of the interrupt routine.

〔effect〕

As described above, according to the present invention, it is possible to efficiently handle interrupt requests from devices that do not have the function of outputting vector numbers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an interrupt control circuit to which the present invention is applied, in which 1 is a CPU, 2 and 3 are I10 devices, 6 is an OR circuit, 8 is a priority encoder, 11 is a level-based interrupt acknowledge detection circuit, 12 is an automatic/external vectoring setting switch for each level, 14 is an OR circuit, 16 is an encoder with a latch, and 18 is a ROM.

Claims (1)

[Claims] An interrupt control device characterized by having a memory that sends a vector number to a microprocessor in place of an interrupt device that does not have a function to output a vector number, and a switch that can set the control for each interrupt level.