JPS63174132A - Interruption controller - Google Patents

Abstract

PURPOSE:To improve universal applicability for complicated interruption control, by providing a control circuit which performs an interruption control operation independently based on a memory which stores information required for the interruption control and the information outputted from the memory. CONSTITUTION:In a ROM14, the information with respect to a vector number, a vectoring method (automatic or external), the presence/absence of the output function of the vector number, and a physical position are et on a prescribed number of address inputs. Also, an interruption control circuit (bus control circuit) 21 performs bus control based on the detection of interruption acknowledge at every level and the information of the output of the ROM14. In other words, the circuit 21, when an automatic vectoring system being indicated by a signal line 16 which represents the system of vectoring, activates a signal line 26, and when an external vectoring system being indicated, is operated by the level of a signal line 17. Thus, by performing the interruption control operation independently based on the information obtained from the ROM14, it is possible to improve the universal applicability for the complicated interruption control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an interrupt control device that responds to interrupt requests from external devices to a microprocessor.

[Prior art]

A vector number is fetched from an external device during the interrupt acknowledge cycle, the start address of the interrupt routine is determined by reading it from a table in memory based on the fetched vector number, and the microprocessor (
There is a method of interrupting the CPU (CPU).

However, I do not have the function to output vector numbers.
In particular, when assigning the same interrupt level to multiple I10 devices or interrupt generation circuits (hereinafter referred to as I10 devices including interrupt generation circuits), a dedicated ROM or the like is provided externally for the purpose of generating vector numbers. Ta.

This vector number generation ROM etc. only sends out vector numbers, and includes automatic vectoring (which automatically issues vector numbers within the CPU) and external vectoring (which automatically issues vector numbers within the CPU). Especially when I10 devices that process with the same interrupt level (one that fetches vector numbers) coexist at the same interrupt level, and even I10 devices that perform the same external vectoring, one with the function of outputting vector numbers and one with vector number generation ROM, etc. Especially if the outputs coexist at the same interrupt level, and even if the I10 device uses the same vectoring method, the one mounted on the same board as the CPU and the one mounted on an external board are especially the same. - In order to perform complex interrupt control such as coexistence at the interrupt level, an I
A circuit for determining the vectoring method of the 10 devices or a circuit for controlling the data bus was further provided to perform interrupt control in accordance with the system.

Therefore, if there is a change in the vectoring method of the I10 device that generates an interrupt, the interrupt control circuit itself must be changed, and such a configuration lacks versatility for interrupt control.

〔the purpose〕

The present invention eliminates the drawbacks of the above-mentioned conventional example and makes it possible to implement the above-mentioned complicated interrupt control using a versatile and simple-configured interrupt control circuit.

〔Example〕

The present invention will be explained below based on preferred embodiments.

FIG. 1 is a block diagram of an embodiment of the present invention.

1 is a CPU, 2 is a priority seat order encoder for interrupts input from i I10 devices lined up at level A, and 3 is a priority seat order encoder for interrupts input from j I10 devices lined up at level B. 4 is a level A common interrupt line output from the priority seat order encoder 2, 5 is a code signal indicating the distinction of i I10 devices lined up at interrupt level A, and 6 is similarly output from the priority seat order encoder 3. However, the level B common interrupt line,
7 is a code signal indicating the distinction between j °I10 devices lined up at interrupt level B.

8 is a priority seat order encoder, 9 is a latch, IO is a three-state output buffer, 11 is an AND circuit, 12 is an i output decoder, and 13 is a j output decoder.

・For 14, the vector number, vectoring method (automatic or external), presence or absence of vector number output function, and physical location (inside or outside the board) have already been set for the specified address input. This is a ROM. Signal lines 15 to 18 are output from the ROM 14,
is the vector number output from the ROM 14, 16 is a signal line indicating the vectoring method (automatic or external), 1
7 is a signal line indicating whether the I10 device has a vector number output function or whether the vector number is sent instead of the ROM 14 when using external vectoring, and 18 is a signal line indicating whether the I10 device has a vector number output function. This is a signal line indicating whether the CPU 1 is on the same board as the CPU 1 or outside the board.

19 is the lower several bits of the address bus that represents the level of the interrupt currently accepted by CPU1, and 20 is the CPU
This is a function code representing the operation of I. 21 is the detection of interrupt acknowledge by level and ROM14
22 is a common enable signal line for the I10 device which has the function of outputting the vector number obtained from the circuit 21; 23 is an interrupt acknowledge signal line for each level; 24 is an enable line for putting the vector number output from the ROM 14 on the data bus, and 25 is an enable line for putting the vector number output by the I10 device outside the board on the data bus inside the board. , 26 is C
A signal line 27 indicates to the PUI that the interrupt targeted by the current interrupt acknowledge cycle is to be executed by automatic vectoring, and a signal line 27 indicates that it is to be executed by external vectoring.

An example of the operation of the first illustrated circuit will be described below.

Assume that one I10 device among i devices with interrupt level A generates an interrupt. This interrupt line is input to the priority seat order encoder 2, and the encoder 2 sends out the code information 5 for this I10 device along with the level A common interrupt line 4. The level A common interrupt line 4 is input to the priority seat order encoder 8, and after being encoded, the CPU
given to.

Based on the output from the encoder 8, when the CPUI becomes able to handle an interrupt, it indicates through the function code 20 that the interrupt acknowledge cycle is in progress, and also uses the lower few bits 19 of the address bus to indicate where the current acceptance is. Indicates the interrupt level. Bus control circuit 2
1, this function code 20 and part 19 of the address contention bus are used to output an interrupt acknowledge signal 23 for each interrupt level.

Assuming that the level of the interrupt currently accepted by the CPUI is A, the interrupt acknowledge signal 2 for each interrupt level
3, only the interrupt acknowledge line for level A becomes active. As a result, the code information 5 for the I10 device is held at its value in the latch 9,
The signal is input to the ROM 14 through the three-state output buffer 10.

The lower number bits 19 of the address bus representing the level of the interrupt currently accepted by the CPUI are input to the ROM 14 in the same way as input to the bus control circuit 21.
By addressing the ROM 14 together with the code information for the I10 device from the three-state output buffer 10, information regarding the interrupt of this ■/○ device 15. 16. 17 and 18 are output.

Here, if the signal line 16 representing the vectoring method indicates that automatic vectoring is to be used, the bus control circuit 21 activates the signal line 26 indicating automatic vectoring to the CPU. . On the other hand, if it is indicated to do it with external vectoring method, then
The following operation is performed depending on the level of the signal line 17 indicating whether this I10 device has a vector number sending function or not.

That is, when using the external vectoring method, if the I10 device has a vector number sending function, the common enable signal line 22 for the I10 device having the vector number output function is activated. As a result, the output of the AND circuit 11 becomes active, and the output of the decoder 1 becomes active.
Enable 2.

Decoder 12 decodes the code signal for the I10 device latched by latch 9, provides an interrupt acknowledge signal to the I10 device that issued the interrupt, and permits transmission of the vector number onto the data bus. Note that the signal line 27 indicating external vectoring to the CPUI is activated by this I10 device.

On the other hand, when performing external vectoring, if the I10 device does not have a vector number sending function, vector number 15 output from the ROM 14 should be sent to the data bus (
Enable signal line 24 to three-state buffer 10
Activate. At the same time, the signal line 27 indicating external vectoring to the CPU is activated.

Regarding the I10 device that has the function of sending vector numbers, are these ■/○ located on the same board as CPU1?
The common enable signal line 22 for the I10 device, which has the function of outputting a vector number when it is indicated that it is inside the board, is activated by the signal line 18 indicating whether it is outside the board, and the operation as described above is performed. Execute. On the other hand, if it is indicated that it is outside the board, the three-state buffer 1 operates simultaneously with the operation when it is inside the board.
Activate the enable signal line 25 to 0. This causes the vector number sent by the off-board I/'O device to appear on the data bus within the CPUI board.

As described above, the control of the interrupt acknowledge cycle for a particular interrupt factor is entirely determined by the information 16, 17 and 18 obtained from the ROM 14.

Therefore, the circuit 21, which is the central entity in interrupt control, is composed of a decoder and a simple gate circuit, and has a small hardware load.

In the above embodiment, the ROM 14 may be a RAM, and by doing so, the vector number, vectoring method, etc. can be stored in the operating status of the system (for example, initial diagnosis operation at power-on, steady operation, abnormality detection operation, etc.). It becomes possible to dynamically change the value depending on the situation, and more versatile interrupt control becomes possible.

〔effect〕

As mentioned above, each ■/○ device that generates an interrupt has a memory that stores information necessary for interrupt control, such as its vectoring method, and in order to perform interrupt control operations independently based on the information from the memory. , changes in the vectoring method for I10 devices can be handled simply by rewriting the contents of the memory. This achieves a highly effective and versatile circuit configuration as the variety of I10 devices that generate interrupts increases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an interrupt control device to which the present invention is applied, in which 1 is a CPU, 2, 3 and 8 are priority seat order encoders, 9 is a latch, IO is a three-state output buffer, 11 is an AND The circuits 12 and 13 are decoders, 14 is a ROM, and 21 is an interrupt control circuit.

Claims (1)

[Claims] An interrupt control device characterized by having a memory that outputs information such as a vectoring method as well as a vector number, and a control circuit that independently controls interrupts for a microprocessor based on the information output from the memory. .