JPS5854462A - Shared memory device - Google Patents

Abstract

PURPOSE:To decrease the packing space and to reduce the cost, by providing a CPU mutual interruption function to a shared memory device. CONSTITUTION:A shared memory 1 is connected to each processor 4 via a port 2 and a memory expander 3, and at the same time a system console 10 is connected to the port 2 within the memory 1. An interrupting flip-flop allotted with a specific settable/resettable memory address from the processor 4 is provided to the port 2 in the memory 1. At the same time, an interruption accepting register which latches the output of the interrupting flip-flop sent from the port 2 is provided to the expander 3 in the processor 4 when no memory accees is carried out. The output of the interruption accepting register is fed to an interruption detecting circuit of the processor 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shared memory device, and more particularly to a shared memory device having a mutual U interrupt function between multiple processing units. Conventional shared memory simply writes and reads data from the CPU, and requires a separate linkage path to provide interrupts between CPUs. Figure 1 shows the structure of the main unit. In Figure 1, 1 is a shared memory;
2 is a shared memory 1, each processing device 4 (CPUI~3)
A processing device connection mechanism (hereinafter referred to as a boat) provided for each
, 3 is a shared memory connection mechanism (hereinafter referred to as a memory expander) provided in each processing device 4 facing the boat 2.
, 5 is an input/output path provided for each processing device 4, 6 is a path expander provided for the input/output path 5, and 7 is a hole 1.
``t8 Ballin'y-Sihas, 9tuJ cage bus controller, 10 system console, 11 shared memory CPU cable, 12 bus/cage path-C
Cable between PUs, 13HlJ/'y-SH~7
This is a cable between stem consoles. In order to issue an interrupt from one CPU to another, first set the data for the interrupt in the shared memory 1 via the memory expander 3, the shared memory CPU-to-CPU cable 11, and the port 2. The bus expander 6 that has received the output command issues an input/output command to the bus expander 6. The bus expander 6 issues an input/output command to the bus expander 6. Port 7, linkage bus 8. The instruction is transferred to the bus expander 6 of the destination CPU via port 7, and the path expander that receives the instruction interrupts the CPU using the same interrupt procedure as other general person output devices. The CPU that receives the 0 interrupt inputs the interrupt data that was previously set on the shared memory and performs the 1 interrupt process. Also.

A stem console 10 is connected to the linkage bus 8, and displays the status of each CPU, activates each CPU/U,
It is possible to issue stop and IPL (initial program load) commands.

In the conventional method, the linkage bus-CPU cable 12
Since a linkage bus mounting unit and a power supply are required, additional space is required and costs are also high.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shared memory device having a phase-q interrupt function between multiple processing units, which requires less space and reduces cost.

The feature of this invention is in the port on the shared memory side.

Each CPU is reset by an interrupt flip-flop assigned to a specific memory address that can be reset. An interrupt acceptance register is provided to latch the output of the interrupt flip 70, and the output of the interrupt acceptance register is sent to the interrupt detection circuit of CP (J).

The practical aspects of the present invention will be explained with reference to FIGS. 2 to 11(2). No. 21A is one side of the entire block of one implementation side of the present invention, and compared to the conventional example (4111), the linkage bus 8,
The linkage bus controller 9, the port 7, the linkage bus to the CPU (Ij cable 12 is absent, and the system console 10 is connected to one of the ports 2 in the shared memory. Here, 24 is a shared memory board. This is a cable between stem consoles.Figure 3 is a block diagram of the shared memory 1 (including port 2) section, and the memory 14
, memory controller 15. It is composed of 16° data bus, 17% control path, and 18% control path. The shared memory CPU-to-CPU cable 11 is composed of a data line 19 and a control line 20.
The shared memory system inter-console cable 24 is composed of a status signal line '21sf-1' line 22 and a control line 23. The fourth cause is CPU4 (
This is a block diagram of a portion of the memory expander (ME) 3. Address bus 2 in the CPU
5. It is composed of a data bus 26%, a control path 27, a register bus 28s, an interrupt request signal x-529, a floating point arithmetic processor 301, a basic arithmetic processor 31, an input/output dedicated processor 32, and a main memory 33°. FIG. 51 shows details of port 2.

The address decoder 46 decodes the address in the common M memory and inputs it to the interrupt flip-flop 34 (34-1, 34-2) or status register (STR, EG) 43 provided for each interrupt level of its own boat. Detects the assigned specific address and outputs the interrupt flip 70 knob selection signal 44
Alternatively, the status register selection signal 45 is turned on. When the shared memory write signal 37 is turned on while the interrupt flip-flop selection signal 44 is turned on, the contents of the shared memory data bus 17 are set in the interrupt flip-flop 34 . The output of this interrupt 79 knob 70 is output when there is no memory access, that is, when the activation request signal 39 is off.
The data line 19 between the shared memory and the CPU is on-bus. An example of on-bus contents is shown in FIG.

In FIG. 5, 35 to 38 are activation request signals (R, EQ) in the shared memory, respectively.

Start reception signal (SEL), write signal (WRJTE),
and a response signal (ANSJ), and 39 to 42 are activation request signals (REQ) between the shared memory CPUs, respectively.
, startup acceptance signal (SEL), write signal (WRITE)
, response signal (ANS).

Further, 47 is an address latch circuit, 48 is a delay circuit for the activation acceptance signal (shared) in the shared memory 49, 52 is an OR gate, 490 to 499 are input/output gates, 501 to 509 are AND gates, and 511° and 512 are inverters. . In FIG. 6, INTO-FF and INTO-FF are interrupt flip-flops 34-1.34 in FIG.
-2 output, and the 15th bit R and UN are CPU
This is a status signal indicating that the is in the R,UN state, and is sent on bus from the memory expander side. In addition, the status register (STREG) is a register i that latches the status of the CPU, and inputs the R and UN signals of bit 15 of the sixth cause from the data bus 19, and when there is no memory access (
When the activation request signal 39 is off), the input contents are passed through to the output, and when the memory is accessed, the previous state is stored. When the specific address assigned to this register is selected, the status register selection signal 45 of the address decoder 46 is turned on, and this output is passed to the shared memory data bus 17.

FIG. 7 shows details of the memory expander 3. The interrupt reception register (INTR, EG) 530 inputs are from the CPU to
When the inter-shared memory data line 19 is connected and there is no memory access (shared memory inter-CPU activation request signal 3
The output of the in-boat interrupt flip-flop which is turned on to the inter-shared data line data line 19 is set by the output pulse of the pulse generating circuit 54, which outputs a pulse only when the common data line 9 is off. The output of the interrupt acceptance register 53 is outputted via the output gate 604 to the interrupt request bus 29 in a wired-OR manner. In addition, the address decoder 55
The access address is related to the memory expander'
(shared memory 1 interrupt flip 70 block, status register, etc.), the memory expander selection signal 60 is turned on. Also, a signal 56 indicating that the CPU is in the RUN state.

When there is no memory access (when the shared memory inter-CPU activation request signal 39 is off), the shared data inter-data line data line 19 is on-passed. In Figure 7, 61-
1.61-2 is an inverter, 601 to 613 are input/output gates, and 701 to 7o5 are AND gates. FIG. 8 shows details of the interrupt receiving section within the basic arithmetic processor 31.

Each signal on the interrupt request bus 29 is connected to AND gates 801 to 80.
After N is logically ANDed with the interrupt mask register 63, it is ORed by the OR gate 800, and becomes the μm sequencer interrupt signal 65, which interrupts the μm sequencer 66. When an interrupt is accepted, in interrupt processing, the interrupt level selection signal (INTLVL 5EL) 64 is turned on, the level is taken into the basic arithmetic logic section 900 via AND gates 901 to 9ON, and the one with the highest priority level is selected. Process. 9th ■ Port 2 for connecting the system console (
sysc) - A specific example is shown. Here, only the essential parts are labeled, and AND gates, OR gates, and input/output gates that are not directly related to understanding the operation are not labeled. This system console connection board) 2 (SY
(for SC) has the following functions (1) to (J).

(1) A function that displays the status of each CPU on the system console.

(21 Function to transfer status control commands from the system console to each CPU.

and (3) a function to transfer system console state control parameters to each CPU.

The first function is realized as follows.

Sequencer 2 activated by fixed-period pulse generator 262
66 counts up the address counter 263, and after updating the address, it is sent to each CPU via the shared memory bus.
Reads the contents of the status register 43 in the port of each CP.
It is set in the state storage register 265 provided for each U. The output of the status storage register 265 is output to the system console and used to display the status of each CPU. The second function is implemented as follows. The sequencer 268 is activated by the state control signal 23 from the system console and uses the address determined by the CPU01 signal 75 and the encoded control signal 23 by the encoder 267 to interrupt the interrupt in the port of the other CPU. Set the flip-flop 34 and
It is possible to provide an interrupt and the activation of various other control functions. However, the interrupt flip-flop referred to here includes not only the normal interrupt level but also levels for controlling the state of the CPU, such as 5TOP and IPL. Next, the third function is realized as follows. When the control parameter signal 74 output from the system console is accessed by each CPU at a specific memory address, the address is detected by the address duder 269 and transferred to the CPU.

In FIG. 9, 70 to 73 are all individual signals, 70 is a startup request signal (R, EQ), 71 is a startup acceptance signal (SEL), 72 is a startup request signal (REQ), and 73 is a startup reception signal. This is a signal (SEL). FIG. 10 shows the interrupt processing procedure. This figure shows a case where a level 0 interrupt is issued from the CPUI to the CPU2. Eleventh, a detailed time chart from the setting of the interrupt flip-flop in FIG. 10 until the interrupt processing is executed and the interrupt flip-flop is reset is shown. As described above, according to the present invention, a shared memory device can have a mutual interrupt function between CPUs with a simple configuration, and the mounting space can be reduced and costs can be reduced.

[Brief explanation of the drawing]

Fig. 1 is an overall block diagram explaining a conventional example, Fig. 2 is an overall block diagram explaining the present invention, and Figs.
Fig. 11 all relate to the present invention, Fig. 3 is a block diagram of the shared memory section, Fig. 4 is a block diagram of the CPU section, Fig. 5 is a detailed explanation of ports, and Fig. 6 is a block diagram of the shared memory section. is c
An explanatory diagram of the format of data between pu and shared memory when the memory is not accessed. Fig. 7 is a detailed explanation of the memory expander. Fig. 8 is a detailed explanatory diagram of the CPU internal interrupt reception unit. Fig. 9 is a detailed explanation of the memory expander. , a detailed explanatory diagram of the port for connecting the system console, FIG. 10 is an explanation of the interrupt procedure, and FIG. 11 is a detailed time chart during one interrupt procedure. 1... Shared memory, 2... Processing device connection m structure, 3.
...Shared memory attachment mechanism, 4...Processing device, 5...
Input/output bus, 11... Shared memory CPU-to-CPU cable, 34... Interrupt flip 70 tube% 43... Status register, '! 81 days JFl 2 z M * + he M E 2 ,,
srs cr o to the horse 4 B horse 56 to ME3 Hiroshi G mouth η '8 Rotomi to the CIO 10th Mi ¥311

Claims (1)

[Claims] 1. One shared memory is provided for multiple processing devices, and the connection between each processing device and the shared memory is provided by a shared memory connection mechanism on the processing device side and a shared memory connection mechanism provided for each processing device on the shared memory side. Processing unit attachments are connected by one-to-one cables, and each processing unit transfers data to and from the shared memory via the shared memory attachment, cable, and process #11 attachment. In a memory device, an interrupt flip-flop that allocates a specific memory address for each interrupt level to the processing device connection mechanism, can be set in the same procedure as accessing shared memory from another processing device, and can be reset from the own processing device. and output means for outputting the output to the data bus between the processing device and the shared memory when the memory is not being accessed, and the shared memory connection mechanism is provided with an output means for outputting the output to the data bus between the processing device and the shared memory when the memory is not being accessed. The feature is that the interrupt reception that sets the contents of the data bus is provided with a register and a transfer means that transfers the output to the interrupt reception circuit in the processing device, realizing a phase U interrupt function between multiple processing devices. shared memory device.